35 lines
1.0 KiB
Plaintext
35 lines
1.0 KiB
Plaintext
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* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
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Required properties:
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- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
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"sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
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- reg : Offset and length of the register set for the device
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- interrupts : Should contain uart interrupt
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- fifosize : Should define hardware rx/tx fifo size
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- clocks : Should contain uart clock number
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Optional properties:
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- uart-has-rtscts: we have hardware flow controller pins in hardware
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- rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
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- cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
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Example:
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uart0: uart@b0050000 {
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cell-index = <0>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0050000 0x1000>;
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interrupts = <17>;
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fifosize = <128>;
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clocks = <&clks 13>;
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};
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On the board-specific dts, we can put rts-gpios and cts-gpios like
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usp@b0090000 {
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compatible = "sirf,prima2-usp-uart";
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uart-has-rtscts;
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rts-gpios = <&gpio 15 0>;
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cts-gpios = <&gpio 46 0>;
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};
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