28 lines
774 B
Plaintext
28 lines
774 B
Plaintext
|
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
|
||
|
|
|
||
|
|
This binding represents the on-chip eFuse OTP controller found on
|
||
|
|
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: should be one of
|
||
|
|
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
|
||
|
|
"fsl,imx6sl-ocotp" (i.MX6SL), or
|
||
|
|
"fsl,imx6sx-ocotp" (i.MX6SX),
|
||
|
|
"fsl,imx6ul-ocotp" (i.MX6UL),
|
||
|
|
"fsl,imx7d-ocotp" (i.MX7D/S),
|
||
|
|
followed by "syscon".
|
||
|
|
- reg: Should contain the register base and length.
|
||
|
|
- clocks: Should contain a phandle pointing to the gated peripheral clock.
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
- read-only: disable write access
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
ocotp: ocotp@21bc000 {
|
||
|
|
compatible = "fsl,imx6q-ocotp", "syscon";
|
||
|
|
reg = <0x021bc000 0x4000>;
|
||
|
|
clocks = <&clks IMX6QDL_CLK_IIM>;
|
||
|
|
read-only;
|
||
|
|
};
|