66 lines
2.6 KiB
Plaintext
66 lines
2.6 KiB
Plaintext
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Renesas R-Car CAN controller Device Tree Bindings
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-------------------------------------------------
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Required properties:
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- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
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"renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
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"renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
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"renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
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"renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC.
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"renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
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"renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
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"renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
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"renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
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"renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
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"renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device.
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"renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: physical base address and size of the R-Car CAN register map.
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- interrupts: interrupt specifier for the sole interrupt.
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- clocks: phandles and clock specifiers for 3 CAN clock inputs.
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- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must be "default".
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Required properties for "renesas,can-r8a7795" and "renesas,can-r8a7796"
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compatible:
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In R8A7795 and R8A7796 SoCs, "clkp2" can be CANFD clock. This is a div6 clock
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and can be used by both CAN and CAN FD controller at the same time. It needs to
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be scaled to maximum frequency if any of these controllers use it. This is done
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using the below properties:
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- assigned-clocks: phandle of clkp2(CANFD) clock.
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- assigned-clock-rates: maximum frequency of this clock.
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Optional properties:
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- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
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<0x0> (default) : Peripheral clock (clkp1)
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<0x1> : Peripheral clock (clkp2)
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<0x3> : Externally input clock
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Example
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-------
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SoC common .dtsi file:
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
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<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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status = "disabled";
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};
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Board specific .dts file:
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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