51 lines
1.5 KiB
Plaintext
51 lines
1.5 KiB
Plaintext
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PXA3xx NAND DT bindings
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Required properties:
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- compatible: Should be set to one of the following:
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marvell,pxa3xx-nand
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marvell,armada370-nand
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marvell,armada-8k-nand
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- reg: The register base for the controller
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- interrupts: The interrupt to map
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- #address-cells: Set to <1> if the node includes partitions
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- marvell,system-controller: Set to retrieve the syscon node that handles
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NAND controller related registers (only required
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with marvell,armada-8k-nand compatible).
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Optional properties:
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- dmas: dma data channel, see dma.txt binding doc
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- marvell,nand-enable-arbiter: Set to enable the bus arbiter
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- marvell,nand-keep-config: Set to keep the NAND controller config as set
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by the bootloader
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- num-cs: Number of chipselect lines to use
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- nand-on-flash-bbt: boolean to enable on flash bbt option if
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not present false
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- nand-ecc-strength: number of bits to correct per ECC step
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- nand-ecc-step-size: number of data bytes covered by a single ECC step
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The following ECC strength and step size are currently supported:
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- nand-ecc-strength = <1>, nand-ecc-step-size = <512>
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- nand-ecc-strength = <4>, nand-ecc-step-size = <512>
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- nand-ecc-strength = <8>, nand-ecc-step-size = <512>
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Example:
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nand0: nand@43100000 {
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compatible = "marvell,pxa3xx-nand";
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reg = <0x43100000 90>;
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interrupts = <45>;
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dmas = <&pdma 97 0>;
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dma-names = "data";
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#address-cells = <1>;
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marvell,nand-enable-arbiter;
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marvell,nand-keep-config;
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num-cs = <1>;
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/* partitions (optional) */
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};
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