53 lines
1.7 KiB
Plaintext
53 lines
1.7 KiB
Plaintext
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* Freescale Enhanced Secure Digital Host Controller (eSDHC)
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The Enhanced Secure Digital Host Controller provides an interface
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for MMC, SD, and SDIO types of memory cards.
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This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-esdhc driver.
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Required properties:
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- compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
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Possible compatibles for PowerPC:
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"fsl,mpc8536-esdhc"
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"fsl,mpc8378-esdhc"
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"fsl,p2020-esdhc"
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"fsl,p4080-esdhc"
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"fsl,t1040-esdhc"
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"fsl,t4240-esdhc"
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Possible compatibles for ARM:
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"fsl,ls1012a-esdhc"
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"fsl,ls1088a-esdhc"
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"fsl,ls1043a-esdhc"
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"fsl,ls1046a-esdhc"
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"fsl,ls2080a-esdhc"
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- interrupt-parent : interrupt source phandle.
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- clock-frequency : specifies eSDHC base clock frequency.
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Optional properties:
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- sdhci,wp-inverted : specifies that eSDHC controller reports
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inverted write-protect state; New devices should use the generic
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"wp-inverted" property.
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- sdhci,1-bit-only : specifies that a controller can only handle
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1-bit data transfers. New devices should use the generic
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"bus-width = <1>" property.
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- sdhci,auto-cmd12: specifies that a controller can only handle auto
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CMD12.
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- voltage-ranges : two cells are required, first cell specifies minimum
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slot voltage (mV), second cell specifies maximum slot voltage (mV).
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Several ranges could be specified.
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- little-endian : If the host controller is little-endian mode, specify
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this property. The default endian mode is big-endian.
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Example:
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sdhci@2e000 {
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compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <42 0x8>;
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interrupt-parent = <&ipic>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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voltage-ranges = <3300 3300>;
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};
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