69 lines
2.8 KiB
Plaintext
69 lines
2.8 KiB
Plaintext
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Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
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Samsung's Exynos architecture contains System MMUs that enables scattered
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physical memory chunks visible as a contiguous region to DMA-capable peripheral
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devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
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System MMU is an IOMMU and supports identical translation table format to
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ARMv7 translation tables with minimum set of page properties including access
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permissions, shareability and security protection. In addition, System MMU has
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another capabilities like L2 TLB or block-fetch buffers to minimize translation
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latency.
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System MMUs are in many to one relation with peripheral devices, i.e. single
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peripheral device might have multiple System MMUs (usually one for each bus
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master), but one System MMU can handle transactions from only one peripheral
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device. The relation between a System MMU and the peripheral device needs to be
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defined in device node of the peripheral device.
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MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
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MMUs.
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* MFC has one System MMU on its left and right bus.
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* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
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for window 1, 2 and 3.
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* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
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the other System MMU on the write channel.
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For information on assigning System MMU controller to its peripheral devices,
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see generic IOMMU bindings.
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Required properties:
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- compatible: Should be "samsung,exynos-sysmmu"
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- reg: A tuple of base address and size of System MMU registers.
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- #iommu-cells: Should be <0>.
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- interrupt-parent: The phandle of the interrupt controller of System MMU
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- interrupts: An interrupt specifier for interrupt signal of System MMU,
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according to the format defined by a particular interrupt
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controller.
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- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
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SYSMMU core clocks.
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Optional "master" if the clock to the System MMU is gated by
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another gate clock other core (usually main gate clock
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of peripheral device this SYSMMU belongs to).
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- clocks: Phandles for respective clocks described by clock-names.
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- power-domains: Required if the System MMU is needed to gate its power.
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Please refer to the following document:
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Documentation/devicetree/bindings/power/pd-samsung.txt
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Examples:
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gsc_0: gsc@13e00000 {
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compatible = "samsung,exynos5-gsc";
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reg = <0x13e00000 0x1000>;
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interrupts = <0 85 0>;
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power-domains = <&pd_gsc>;
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clocks = <&clock CLK_GSCL0>;
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clock-names = "gscl";
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iommus = <&sysmmu_gsc0>;
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};
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sysmmu_gsc0: sysmmu@13E80000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E80000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
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power-domains = <&pd_gsc>;
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#iommu-cells = <0>;
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};
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