78 lines
3.3 KiB
Plaintext
78 lines
3.3 KiB
Plaintext
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* ARM SMMUv3 Architecture Implementation
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The SMMUv3 architecture is a significant departure from previous
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revisions, replacing the MMIO register interface with in-memory command
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and event queues and adding support for the ATS and PRI components of
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the PCIe specification.
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** SMMUv3 required properties:
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- compatible : Should include:
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* "arm,smmu-v3" for any SMMUv3 compliant
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implementation. This entry should be last in the
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compatible list.
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- reg : Base address and size of the SMMU.
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- interrupts : Non-secure interrupt list describing the wired
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interrupt sources corresponding to entries in
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interrupt-names. If no wired interrupts are
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present then this property may be omitted.
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- interrupt-names : When the interrupts property is present, should
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include the following:
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* "eventq" - Event Queue not empty
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* "priq" - PRI Queue not empty
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* "cmdq-sync" - CMD_SYNC complete
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* "gerror" - Global Error activated
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* "combined" - The combined interrupt is optional,
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and should only be provided if the
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hardware supports just a single,
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combined interrupt line.
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If provided, then the combined interrupt
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will be used in preference to any others.
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- #iommu-cells : See the generic IOMMU binding described in
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devicetree/bindings/pci/pci-iommu.txt
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for details. For SMMUv3, must be 1, with each cell
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describing a single stream ID. All possible stream
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IDs which a device may emit must be described.
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** SMMUv3 optional properties:
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- dma-coherent : Present if DMA operations made by the SMMU (page
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table walks, stream table accesses etc) are cache
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coherent with the CPU.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- msi-parent : See the generic MSI binding described in
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devicetree/bindings/interrupt-controller/msi.txt
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for a description of the msi-parent property.
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- hisilicon,broken-prefetch-cmd
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: Avoid sending CMD_PREFETCH_* commands to the SMMU.
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- cavium,cn9900-broken-page1-regspace
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: Replaces all page 1 offsets used for EVTQ_PROD/CONS,
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PRIQ_PROD/CONS register access with page 0 offsets.
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Set for Cavium ThunderX2 silicon that doesn't support
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SMMU page1 register space.
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** Example
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smmu@2b400000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x2b400000 0x0 0x20000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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dma-coherent;
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#iommu-cells = <1>;
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msi-parent = <&its 0xff0000>;
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};
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