52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
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Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs.
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Required Properties:
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- #address-cells : should be 1
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- #size-cells : should be 0
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- reg : address offset and range of bus
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- compatible : should be "aspeed,ast2400-i2c-bus"
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or "aspeed,ast2500-i2c-bus"
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- clocks : root clock of bus, should reference the APB
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clock in the second cell
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- resets : phandle to reset controller with the reset number in
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the second cell
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- interrupts : interrupt number
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- interrupt-parent : interrupt controller for bus, should reference a
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aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic
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interrupt controller
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Optional Properties:
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- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
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specified
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- multi-master : states that there is another master active on this bus.
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Example:
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i2c {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1e78a000 0x1000>;
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i2c_ic: interrupt-controller@0 {
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#interrupt-cells = <1>;
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compatible = "aspeed,ast2400-i2c-ic";
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reg = <0x0 0x40>;
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interrupts = <12>;
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interrupt-controller;
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};
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i2c0: i2c-bus@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x40 0x40>;
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compatible = "aspeed,ast2400-i2c-bus";
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clocks = <&syscon ASPEED_CLK_APB>;
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resets = <&syscon ASPEED_RESET_I2C>;
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bus-frequency = <100000>;
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interrupts = <0>;
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interrupt-parent = <&i2c_ic>;
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};
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};
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