121 lines
3.9 KiB
Plaintext
121 lines
3.9 KiB
Plaintext
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LVDS Display Panel
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==================
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LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
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incompatible data link layers have been used over time to transmit image data
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to LVDS panels. This bindings supports display panels compatible with the
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following specifications.
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[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
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1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
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[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
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Semiconductor
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[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
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Electronics Standards Association (VESA)
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Device compatible with those specifications have been marketed under the
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FPD-Link and FlatLink brands.
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Required properties:
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- compatible: Shall contain "panel-lvds" in addition to a mandatory
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panel-specific compatible string defined in individual panel bindings. The
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"panel-lvds" value shall never be used on its own.
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- width-mm: See panel-common.txt.
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- height-mm: See panel-common.txt.
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- data-mapping: The color signals mapping order, "jeida-18", "jeida-24"
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or "vesa-24".
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Optional properties:
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- label: See panel-common.txt.
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- gpios: See panel-common.txt.
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- backlight: See panel-common.txt.
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- data-mirror: If set, reverse the bit order described in the data mappings
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below on all data lanes, transmitting bits for slots 6 to 0 instead of
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0 to 6.
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Required nodes:
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- panel-timing: See panel-common.txt.
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- ports: See panel-common.txt. These bindings require a single port subnode
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corresponding to the panel LVDS input.
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LVDS data mappings are defined as follows.
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- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
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[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
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DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
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specifications. Data are transferred as follows on 4 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
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DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
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DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
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- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
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Data are transferred as follows on 4 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
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DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
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Control signals are mapped as follows.
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CTL0: HSync
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CTL1: VSync
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CTL2: Data Enable
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CTL3: 0
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Example
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-------
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panel {
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compatible = "mitsubishi,aa121td01", "panel-lvds";
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width-mm = <261>;
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height-mm = <163>;
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data-mapping = "jeida-24";
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panel-timing {
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/* 1280x800 @60Hz */
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clock-frequency = <71000000>;
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hactive = <1280>;
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vactive = <800>;
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hsync-len = <70>;
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hfront-porch = <20>;
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hback-porch = <70>;
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vsync-len = <5>;
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vfront-porch = <3>;
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vback-porch = <15>;
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};
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port {
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panel_in: endpoint {
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remote-endpoint = <&lvds_encoder>;
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};
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};
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};
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