171 lines
6.2 KiB
Plaintext
171 lines
6.2 KiB
Plaintext
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This binding is a work-in-progress, and are based on some experimental
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work by benh[1].
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Sources of clock signal can be represented by any node in the device
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tree. Those nodes are designated as clock providers. Clock consumer
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nodes use a phandle and clock specifier pair to connect clock provider
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outputs to clock inputs. Similar to the gpio specifiers, a clock
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specifier is an array of zero, one or more cells identifying the clock
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output on a device. The length of a clock specifier is defined by the
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value of a #clock-cells property in the clock provider node.
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[1] http://patchwork.ozlabs.org/patch/31551/
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==Clock providers==
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Required properties:
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#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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with a single clock output and 1 for nodes with multiple
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clock outputs.
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Optional properties:
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clock-output-names: Recommended to be a list of strings of clock output signal
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names indexed by the first cell in the clock specifier.
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However, the meaning of clock-output-names is domain
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specific to the clock provider, and is only provided to
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encourage using the same meaning for the majority of clock
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providers. This format may not work for clock providers
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using a complex clock specifier format. In those cases it
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is recommended to omit this property and create a binding
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specific names property.
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Clock consumer nodes must never directly reference
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the provider's clock-output-names property.
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For example:
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oscillator {
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#clock-cells = <1>;
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clock-output-names = "ckil", "ckih";
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};
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- this node defines a device with two clock outputs, the first named
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"ckil" and the second named "ckih". Consumer nodes always reference
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clocks by index. The names should reflect the clock output signal
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names for the device.
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clock-indices: If the identifying number for the clocks in the node
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is not linear from zero, then this allows the mapping of
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identifiers into the clock-output-names array.
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For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
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oscillator {
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compatible = "myclocktype";
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#clock-cells = <1>;
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clock-indices = <1>, <3>;
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clock-output-names = "clka", "clkb";
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}
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This ensures we do not have any empty strings in clock-output-names
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==Clock consumers==
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Required properties:
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clocks: List of phandle and clock specifier pairs, one pair
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for each clock input to the device. Note: if the
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clock provider specifies '0' for #clock-cells, then
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only the phandle portion of the pair will appear.
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Optional properties:
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clock-names: List of clock input name strings sorted in the same
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order as the clocks property. Consumers drivers
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will use clock-names to match clock input names
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with clocks specifiers.
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clock-ranges: Empty property indicating that child nodes can inherit named
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clocks from this node. Useful for bus nodes to provide a
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clock to their children.
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For example:
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device {
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clocks = <&osc 1>, <&ref 0>;
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clock-names = "baud", "register";
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};
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This represents a device with two clock inputs, named "baud" and "register".
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The baud clock is connected to output 1 of the &osc device, and the register
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clock is connected to output 0 of the &ref.
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==Example==
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/* external oscillator */
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <32678>;
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clock-output-names = "osc";
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};
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/* phase-locked-loop device, generates a higher frequency clock
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* from the external oscillator reference */
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pll: pll@4c000 {
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compatible = "vendor,some-pll-interface"
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#clock-cells = <1>;
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clocks = <&osc 0>;
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clock-names = "ref";
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reg = <0x4c000 0x1000>;
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clock-output-names = "pll", "pll-switched";
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};
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/* UART, using the low frequency oscillator for the baud clock,
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* and the high frequency switched PLL output for register
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* clocking */
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uart@a000 {
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compatible = "fsl,imx-uart";
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reg = <0xa000 0x1000>;
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interrupts = <33>;
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clocks = <&osc 0>, <&pll 1>;
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clock-names = "baud", "register";
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};
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This DT fragment defines three devices: an external oscillator to provide a
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low-frequency reference clock, a PLL device to generate a higher frequency
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clock signal, and a UART.
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* The oscillator is fixed-frequency, and provides one clock output, named "osc".
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* The PLL is both a clock provider and a clock consumer. It uses the clock
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signal generated by the external oscillator, and provides two output signals
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("pll" and "pll-switched").
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* The UART has its baud clock connected the external oscillator and its
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register clock connected to the PLL clock (the "pll-switched" signal)
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==Assigned clock parents and rates==
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Some platforms may require initial configuration of default parent clocks
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and clock frequencies. Such a configuration can be specified in a device tree
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node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
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properties. The assigned-clock-parents property should contain a list of parent
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clocks in the form of a phandle and clock specifier pair and the
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assigned-clock-rates property should contain a list of frequencies in Hz. Both
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these properties should correspond to the clocks listed in the assigned-clocks
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property.
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To skip setting parent or rate of a clock its corresponding entry should be
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set to 0, or can be omitted if it is not followed by any non-zero entry.
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uart@a000 {
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compatible = "fsl,imx-uart";
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reg = <0xa000 0x1000>;
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...
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clocks = <&osc 0>, <&pll 1>;
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clock-names = "baud", "register";
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assigned-clocks = <&clkcon 0>, <&pll 2>;
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assigned-clock-parents = <&pll 2>;
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assigned-clock-rates = <0>, <460800>;
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};
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In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
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the <&pll 2> clock is assigned a frequency value of 460800 Hz.
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Configuring a clock's parent and rate through the device node that consumes
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the clock can be done only for clocks that have a single user. Specifying
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conflicting parent or rate configuration in multiple consumer nodes for
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a shared clock is forbidden.
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Configuration of common clocks, which affect multiple consumer devices can
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be similarly specified in the clock provider node.
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