348 lines
8.2 KiB
C
348 lines
8.2 KiB
C
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/*
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* Au1000/Au1500/Au1100 AC97C controller driver for ASoC
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*
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* (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
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*
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* based on the old ALSA driver originally written by
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* Charles Eidsness <charles@cooper-street.com>
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/suspend.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/mach-au1x00/au1000.h>
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#include "psc.h"
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/* register offsets and bits */
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#define AC97_CONFIG 0x00
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#define AC97_STATUS 0x04
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#define AC97_DATA 0x08
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#define AC97_CMDRESP 0x0c
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#define AC97_ENABLE 0x10
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#define CFG_RC(x) (((x) & 0x3ff) << 13) /* valid rx slots mask */
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#define CFG_XS(x) (((x) & 0x3ff) << 3) /* valid tx slots mask */
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#define CFG_SG (1 << 2) /* sync gate */
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#define CFG_SN (1 << 1) /* sync control */
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#define CFG_RS (1 << 0) /* acrst# control */
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#define STAT_XU (1 << 11) /* tx underflow */
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#define STAT_XO (1 << 10) /* tx overflow */
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#define STAT_RU (1 << 9) /* rx underflow */
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#define STAT_RO (1 << 8) /* rx overflow */
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#define STAT_RD (1 << 7) /* codec ready */
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#define STAT_CP (1 << 6) /* command pending */
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#define STAT_TE (1 << 4) /* tx fifo empty */
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#define STAT_TF (1 << 3) /* tx fifo full */
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#define STAT_RE (1 << 1) /* rx fifo empty */
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#define STAT_RF (1 << 0) /* rx fifo full */
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#define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
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#define CMD_GET_DATA(x) ((x) & 0xffff)
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#define CMD_READ (1 << 7)
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#define CMD_WRITE (0 << 7)
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#define CMD_IDX(x) ((x) & 0x7f)
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#define EN_D (1 << 1) /* DISable bit */
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#define EN_CE (1 << 0) /* clock enable bit */
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/* how often to retry failed codec register reads/writes */
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#define AC97_RW_RETRIES 5
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#define AC97_RATES \
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SNDRV_PCM_RATE_CONTINUOUS
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#define AC97_FMTS \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
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/* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
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* once AC97C on early Alchemy chips. The newer ones aren't so lucky.
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*/
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static struct au1xpsc_audio_data *ac97c_workdata;
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#define ac97_to_ctx(x) ac97c_workdata
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static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
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{
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return __raw_readl(ctx->mmio + reg);
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}
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static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
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{
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__raw_writel(v, ctx->mmio + reg);
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wmb();
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}
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static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
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unsigned short r)
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{
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struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
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unsigned int tmo, retry;
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unsigned long data;
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data = ~0;
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&ctx->lock);
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tmo = 5;
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while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
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udelay(21); /* wait an ac97 frame time */
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if (!tmo) {
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pr_debug("ac97rd timeout #1\n");
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goto next;
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}
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WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
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/* stupid errata: data is only valid for 21us, so
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* poll, Forrest, poll...
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*/
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tmo = 0x10000;
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while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
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asm volatile ("nop");
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data = RD(ctx, AC97_CMDRESP);
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if (!tmo)
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pr_debug("ac97rd timeout #2\n");
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next:
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mutex_unlock(&ctx->lock);
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} while (--retry && !tmo);
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pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
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return retry ? data & 0xffff : 0xffff;
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}
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static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
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unsigned short v)
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{
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struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
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unsigned int tmo, retry;
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&ctx->lock);
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for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
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udelay(21);
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if (!tmo) {
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pr_debug("ac97wr timeout #1\n");
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goto next;
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}
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WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
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for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
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udelay(21);
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if (!tmo)
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pr_debug("ac97wr timeout #2\n");
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next:
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mutex_unlock(&ctx->lock);
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} while (--retry && !tmo);
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pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
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}
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static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
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WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
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msleep(20);
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WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
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WR(ctx, AC97_CONFIG, ctx->cfg);
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}
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static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
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int i;
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WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
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msleep(500);
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WR(ctx, AC97_CONFIG, ctx->cfg);
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/* wait for codec ready */
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i = 50;
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while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
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msleep(20);
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if (!i)
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printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
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}
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/* AC97 controller operations */
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static struct snd_ac97_bus_ops ac97c_bus_ops = {
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.read = au1xac97c_ac97_read,
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.write = au1xac97c_ac97_write,
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.reset = au1xac97c_ac97_cold_reset,
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.warm_reset = au1xac97c_ac97_warm_reset,
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};
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static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
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return 0;
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}
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static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
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.startup = alchemy_ac97c_startup,
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};
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static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
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{
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return ac97c_workdata ? 0 : -ENODEV;
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}
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static struct snd_soc_dai_driver au1xac97c_dai_driver = {
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.name = "alchemy-ac97c",
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.bus_control = true,
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.probe = au1xac97c_dai_probe,
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.playback = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.capture = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.ops = &alchemy_ac97c_ops,
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};
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static const struct snd_soc_component_driver au1xac97c_component = {
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.name = "au1xac97c",
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};
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static int au1xac97c_drvprobe(struct platform_device *pdev)
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{
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int ret;
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struct resource *iores, *dmares;
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struct au1xpsc_audio_data *ctx;
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ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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mutex_init(&ctx->lock);
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, iores->start,
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resource_size(iores),
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pdev->name))
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return -EBUSY;
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ctx->mmio = devm_ioremap_nocache(&pdev->dev, iores->start,
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resource_size(iores));
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if (!ctx->mmio)
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return -EBUSY;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!dmares)
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return -EBUSY;
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ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (!dmares)
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return -EBUSY;
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ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
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/* switch it on */
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WR(ctx, AC97_ENABLE, EN_D | EN_CE);
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WR(ctx, AC97_ENABLE, EN_CE);
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ctx->cfg = CFG_RC(3) | CFG_XS(3);
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WR(ctx, AC97_CONFIG, ctx->cfg);
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platform_set_drvdata(pdev, ctx);
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ret = snd_soc_set_ac97_ops(&ac97c_bus_ops);
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if (ret)
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return ret;
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ret = snd_soc_register_component(&pdev->dev, &au1xac97c_component,
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&au1xac97c_dai_driver, 1);
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if (ret)
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return ret;
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ac97c_workdata = ctx;
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return 0;
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}
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static int au1xac97c_drvremove(struct platform_device *pdev)
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{
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struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
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snd_soc_unregister_component(&pdev->dev);
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WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
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ac97c_workdata = NULL; /* MDEV */
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return 0;
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}
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#ifdef CONFIG_PM
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static int au1xac97c_drvsuspend(struct device *dev)
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{
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struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
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WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
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return 0;
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}
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static int au1xac97c_drvresume(struct device *dev)
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{
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struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
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WR(ctx, AC97_ENABLE, EN_D | EN_CE);
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WR(ctx, AC97_ENABLE, EN_CE);
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WR(ctx, AC97_CONFIG, ctx->cfg);
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return 0;
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}
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static const struct dev_pm_ops au1xpscac97_pmops = {
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.suspend = au1xac97c_drvsuspend,
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.resume = au1xac97c_drvresume,
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};
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#define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
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#else
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#define AU1XPSCAC97_PMOPS NULL
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#endif
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static struct platform_driver au1xac97c_driver = {
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.driver = {
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.name = "alchemy-ac97c",
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.pm = AU1XPSCAC97_PMOPS,
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},
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.probe = au1xac97c_drvprobe,
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.remove = au1xac97c_drvremove,
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};
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module_platform_driver(au1xac97c_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
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MODULE_AUTHOR("Manuel Lauss");
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