419 lines
15 KiB
C
419 lines
15 KiB
C
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/*
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* Copyright (c) 2014-2017 Intel Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if !defined(OPA_PORT_INFO_H)
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#define OPA_PORT_INFO_H
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#define OPA_PORT_LINK_MODE_NOP 0 /* No change */
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#define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
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#define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */
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#define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */
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#define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
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#define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
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#define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */
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#define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */
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#define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
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#define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
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#define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
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#define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
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/* Link Down / Neighbor Link Down Reason; indicated as follows: */
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#define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */
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#define OPA_LINKDOWN_REASON_RCV_ERROR_0 1
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#define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
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#define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
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#define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
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#define OPA_LINKDOWN_REASON_BAD_SLID 5
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#define OPA_LINKDOWN_REASON_BAD_DLID 6
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#define OPA_LINKDOWN_REASON_BAD_L2 7
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#define OPA_LINKDOWN_REASON_BAD_SC 8
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#define OPA_LINKDOWN_REASON_RCV_ERROR_8 9
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#define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
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#define OPA_LINKDOWN_REASON_RCV_ERROR_10 11
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#define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12
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#define OPA_LINKDOWN_REASON_PREEMPT_VL15 13
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#define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14
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#define OPA_LINKDOWN_REASON_RCV_ERROR_14 15
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#define OPA_LINKDOWN_REASON_RCV_ERROR_15 16
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#define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17
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#define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18
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#define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19
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#define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20
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#define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21
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#define OPA_LINKDOWN_REASON_BAD_PREEMPT 22
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#define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23
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#define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24
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#define OPA_LINKDOWN_REASON_RCV_ERROR_24 25
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#define OPA_LINKDOWN_REASON_RCV_ERROR_25 26
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#define OPA_LINKDOWN_REASON_RCV_ERROR_26 27
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#define OPA_LINKDOWN_REASON_RCV_ERROR_27 28
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#define OPA_LINKDOWN_REASON_RCV_ERROR_28 29
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#define OPA_LINKDOWN_REASON_RCV_ERROR_29 30
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#define OPA_LINKDOWN_REASON_RCV_ERROR_30 31
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#define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32
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#define OPA_LINKDOWN_REASON_UNKNOWN 33
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/* 34 -reserved */
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#define OPA_LINKDOWN_REASON_REBOOT 35
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#define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36
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/* 37-38 reserved */
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#define OPA_LINKDOWN_REASON_FM_BOUNCE 39
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#define OPA_LINKDOWN_REASON_SPEED_POLICY 40
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#define OPA_LINKDOWN_REASON_WIDTH_POLICY 41
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/* 42-48 reserved */
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#define OPA_LINKDOWN_REASON_DISCONNECTED 49
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#define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50
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#define OPA_LINKDOWN_REASON_NOT_INSTALLED 51
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#define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52
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/* 53 reserved */
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#define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54
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/* 55 reserved */
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#define OPA_LINKDOWN_REASON_POWER_POLICY 56
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#define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57
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#define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58
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/* 59 reserved */
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#define OPA_LINKDOWN_REASON_SWITCH_MGMT 60
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#define OPA_LINKDOWN_REASON_SMA_DISABLED 61
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/* 62 reserved */
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#define OPA_LINKDOWN_REASON_TRANSIENT 63
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/* 64-255 reserved */
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/* OPA Link Init reason; indicated as follows: */
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/* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
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#define OPA_LINKINIT_REASON_NOP 0
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#define OPA_LINKINIT_REASON_LINKUP (1 << 4)
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#define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
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#define OPA_LINKINIT_REASON_CLEAR (8 << 4)
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#define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4)
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#define OPA_LINKINIT_QUARANTINED (9 << 4)
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#define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4)
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#define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
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#define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
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#define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
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#define OPA_LINK_WIDTH_1X 0x0001
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#define OPA_LINK_WIDTH_2X 0x0002
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#define OPA_LINK_WIDTH_3X 0x0004
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#define OPA_LINK_WIDTH_4X 0x0008
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#define OPA_CAP_MASK3_IsEthOnFabricSupported (1 << 13)
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#define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
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#define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
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#define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
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#define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4)
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#define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
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/* reserved (1 << 2) */
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#define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1)
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#define OPA_CAP_MASK3_IsVLrSupported (1 << 0)
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/**
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* new MTU values
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*/
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enum {
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OPA_MTU_8192 = 6,
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OPA_MTU_10240 = 7,
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};
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enum {
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OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
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OPA_PORT_PHYS_CONF_STANDARD = 1,
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OPA_PORT_PHYS_CONF_FIXED = 2,
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OPA_PORT_PHYS_CONF_VARIABLE = 3,
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OPA_PORT_PHYS_CONF_SI_PHOTO = 4
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};
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enum port_info_field_masks {
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/* vl.cap */
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OPA_PI_MASK_VL_CAP = 0x1F,
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/* port_states.ledenable_offlinereason */
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OPA_PI_MASK_OFFLINE_REASON = 0x0F,
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OPA_PI_MASK_LED_ENABLE = 0x40,
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/* port_states.unsleepstate_downdefstate */
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OPA_PI_MASK_UNSLEEP_STATE = 0xF0,
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OPA_PI_MASK_DOWNDEF_STATE = 0x0F,
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/* port_states.portphysstate_portstate */
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OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0,
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OPA_PI_MASK_PORT_STATE = 0x0F,
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/* port_phys_conf */
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OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F,
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/* collectivemask_multicastmask */
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OPA_PI_MASK_COLLECT_MASK = 0x38,
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OPA_PI_MASK_MULTICAST_MASK = 0x07,
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/* mkeyprotect_lmc */
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OPA_PI_MASK_MKEY_PROT_BIT = 0xC0,
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OPA_PI_MASK_LMC = 0x0F,
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/* smsl */
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OPA_PI_MASK_SMSL = 0x1F,
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/* partenforce_filterraw */
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/* Filter Raw In/Out bits 1 and 2 were removed */
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OPA_PI_MASK_LINKINIT_REASON = 0xF0,
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OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08,
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OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04,
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/* operational_vls */
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OPA_PI_MASK_OPERATIONAL_VL = 0x1F,
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/* sa_qp */
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OPA_PI_MASK_SA_QP = 0x00FFFFFF,
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/* sm_trap_qp */
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OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF,
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/* localphy_overrun_errors */
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OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0,
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OPA_PI_MASK_OVERRUN_ERRORS = 0x0F,
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/* clientrereg_subnettimeout */
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OPA_PI_MASK_CLIENT_REREGISTER = 0x80,
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OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F,
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/* port_link_mode */
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OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10),
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OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
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OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0),
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/* port_link_crc_mode */
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OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00,
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OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0,
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OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F,
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/* port_mode */
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OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001,
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OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002,
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OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004,
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OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008,
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OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010,
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OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020,
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OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040,
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/* flit_control.interleave */
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OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12),
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OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10),
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OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
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OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0),
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/* port_error_action */
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OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000,
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/* 7 bits reserved */
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OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000,
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OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000,
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OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000,
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OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000,
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OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000,
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OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000,
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OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000,
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OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000,
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/* 2 bits reserved */
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OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000,
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OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000,
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OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800,
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/* 1 bit reserved */
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OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200,
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/* 1 bit reserved */
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OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080,
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OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040,
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OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020,
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OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010,
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OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008,
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OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004,
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OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002,
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OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001,
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/* pass_through.res_drctl */
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OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01,
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/* buffer_units */
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OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11),
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OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
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OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
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OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0),
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/* neigh_mtu.pvlx_to_mtu */
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OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0,
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OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F,
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/* neigh_mtu.vlstall_hoq_life */
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OPA_PI_MASK_VL_STALL = (0x03 << 5),
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OPA_PI_MASK_HOQ_LIFE = (0x1F << 0),
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/* port_neigh_mode */
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OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
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OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2),
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OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0),
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/* resptime_value */
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OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F,
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/* mtucap */
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OPA_PI_MASK_MTU_CAP = 0x0F,
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};
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struct opa_port_states {
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u8 reserved;
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u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
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u8 reserved2;
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u8 portphysstate_portstate; /* 4 bits, 4 bits */
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};
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struct opa_port_state_info {
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struct opa_port_states port_states;
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__be16 link_width_downgrade_tx_active;
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__be16 link_width_downgrade_rx_active;
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};
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struct opa_port_info {
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__be32 lid;
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__be32 flow_control_mask;
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struct {
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u8 res; /* was inittype */
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u8 cap; /* 3 res, 5 bits */
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||
|
|
__be16 high_limit;
|
||
|
|
__be16 preempt_limit;
|
||
|
|
u8 arb_high_cap;
|
||
|
|
u8 arb_low_cap;
|
||
|
|
} vl;
|
||
|
|
|
||
|
|
struct opa_port_states port_states;
|
||
|
|
u8 port_phys_conf; /* 4 res, 4 bits */
|
||
|
|
u8 collectivemask_multicastmask; /* 2 res, 3, 3 */
|
||
|
|
u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */
|
||
|
|
u8 smsl; /* 3 res, 5 bits */
|
||
|
|
|
||
|
|
u8 partenforce_filterraw; /* bit fields */
|
||
|
|
u8 operational_vls; /* 3 res, 5 bits */
|
||
|
|
__be16 pkey_8b;
|
||
|
|
__be16 pkey_10b;
|
||
|
|
__be16 mkey_violations;
|
||
|
|
|
||
|
|
__be16 pkey_violations;
|
||
|
|
__be16 qkey_violations;
|
||
|
|
__be32 sm_trap_qp; /* 8 bits, 24 bits */
|
||
|
|
|
||
|
|
__be32 sa_qp; /* 8 bits, 24 bits */
|
||
|
|
u8 neigh_port_num;
|
||
|
|
u8 link_down_reason;
|
||
|
|
u8 neigh_link_down_reason;
|
||
|
|
u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */
|
||
|
|
|
||
|
|
struct {
|
||
|
|
__be16 supported;
|
||
|
|
__be16 enabled;
|
||
|
|
__be16 active;
|
||
|
|
} link_speed;
|
||
|
|
struct {
|
||
|
|
__be16 supported;
|
||
|
|
__be16 enabled;
|
||
|
|
__be16 active;
|
||
|
|
} link_width;
|
||
|
|
struct {
|
||
|
|
__be16 supported;
|
||
|
|
__be16 enabled;
|
||
|
|
__be16 tx_active;
|
||
|
|
__be16 rx_active;
|
||
|
|
} link_width_downgrade;
|
||
|
|
__be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */
|
||
|
|
__be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */
|
||
|
|
|
||
|
|
__be16 port_mode; /* 9 res, bit fields */
|
||
|
|
struct {
|
||
|
|
__be16 supported;
|
||
|
|
__be16 enabled;
|
||
|
|
} port_packet_format;
|
||
|
|
struct {
|
||
|
|
__be16 interleave; /* 2 res, 2,2,5,5 */
|
||
|
|
struct {
|
||
|
|
__be16 min_initial;
|
||
|
|
__be16 min_tail;
|
||
|
|
u8 large_pkt_limit;
|
||
|
|
u8 small_pkt_limit;
|
||
|
|
u8 max_small_pkt_limit;
|
||
|
|
u8 preemption_limit;
|
||
|
|
} preemption;
|
||
|
|
} flit_control;
|
||
|
|
|
||
|
|
__be32 reserved4;
|
||
|
|
__be32 port_error_action; /* bit field */
|
||
|
|
|
||
|
|
struct {
|
||
|
|
u8 egress_port;
|
||
|
|
u8 res_drctl; /* 7 res, 1 */
|
||
|
|
} pass_through;
|
||
|
|
__be16 mkey_lease_period;
|
||
|
|
__be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
|
||
|
|
|
||
|
|
__be32 reserved5;
|
||
|
|
__be32 sm_lid;
|
||
|
|
|
||
|
|
__be64 mkey;
|
||
|
|
|
||
|
|
__be64 subnet_prefix;
|
||
|
|
|
||
|
|
struct {
|
||
|
|
u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
|
||
|
|
} neigh_mtu;
|
||
|
|
|
||
|
|
struct {
|
||
|
|
u8 vlstall_hoqlife; /* 3 bits, 5 bits */
|
||
|
|
} xmit_q[OPA_MAX_VLS];
|
||
|
|
|
||
|
|
struct {
|
||
|
|
u8 addr[16];
|
||
|
|
} ipaddr_ipv6;
|
||
|
|
|
||
|
|
struct {
|
||
|
|
u8 addr[4];
|
||
|
|
} ipaddr_ipv4;
|
||
|
|
|
||
|
|
u32 reserved6;
|
||
|
|
u32 reserved7;
|
||
|
|
u32 reserved8;
|
||
|
|
|
||
|
|
__be64 neigh_node_guid;
|
||
|
|
|
||
|
|
__be32 ib_cap_mask;
|
||
|
|
__be16 reserved9; /* was ib_cap_mask2 */
|
||
|
|
__be16 opa_cap_mask;
|
||
|
|
|
||
|
|
__be32 reserved10; /* was link_roundtrip_latency */
|
||
|
|
__be16 overall_buffer_space;
|
||
|
|
__be16 reserved11; /* was max_credit_hint */
|
||
|
|
|
||
|
|
__be16 diag_code;
|
||
|
|
struct {
|
||
|
|
u8 buffer;
|
||
|
|
u8 wire;
|
||
|
|
} replay_depth;
|
||
|
|
u8 port_neigh_mode;
|
||
|
|
u8 mtucap; /* 4 res, 4 bits */
|
||
|
|
|
||
|
|
u8 resptimevalue; /* 3 res, 5 bits */
|
||
|
|
u8 local_port_num;
|
||
|
|
u8 reserved12;
|
||
|
|
u8 reserved13; /* was guid_cap */
|
||
|
|
} __attribute__ ((packed));
|
||
|
|
|
||
|
|
#endif /* OPA_PORT_INFO_H */
|