70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
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/*
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* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#ifndef _DT_BINDINGS_CLK_SUNIV_H_
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#define _DT_BINDINGS_CLK_SUNIV_H_
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#define CLK_CPU 11
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#define CLK_BUS_MMC0 14
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#define CLK_BUS_MMC1 15
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#define CLK_BUS_DRAM 16
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#define CLK_BUS_SPI0 17
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#define CLK_BUS_SPI1 18
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#define CLK_BUS_OTG 19
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#define CLK_BUS_VE 20
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#define CLK_BUS_LCD 21
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#define CLK_BUS_DEINTERLACE 22
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#define CLK_BUS_CSI 23
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#define CLK_BUS_TVD 24
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#define CLK_BUS_TVE 25
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#define CLK_BUS_DE_BE 26
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#define CLK_BUS_DE_FE 27
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#define CLK_BUS_CODEC 28
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#define CLK_BUS_SPDIF 29
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#define CLK_BUS_IR 30
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#define CLK_BUS_RSB 31
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#define CLK_BUS_I2S0 32
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#define CLK_BUS_I2C0 33
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#define CLK_BUS_I2C1 34
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#define CLK_BUS_I2C2 35
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#define CLK_BUS_PIO 36
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#define CLK_BUS_UART0 37
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#define CLK_BUS_UART1 38
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#define CLK_BUS_UART2 39
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#define CLK_MMC0 40
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#define CLK_MMC0_SAMPLE 41
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#define CLK_MMC0_OUTPUT 42
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#define CLK_MMC1 43
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#define CLK_MMC1_SAMPLE 44
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#define CLK_MMC1_OUTPUT 45
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#define CLK_I2S 46
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#define CLK_SPDIF 47
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#define CLK_USB_PHY0 48
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#define CLK_DRAM_VE 49
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#define CLK_DRAM_CSI 50
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#define CLK_DRAM_DEINTERLACE 51
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#define CLK_DRAM_TVD 52
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#define CLK_DRAM_DE_FE 53
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#define CLK_DRAM_DE_BE 54
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#define CLK_DE_BE 55
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#define CLK_DE_FE 56
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#define CLK_TCON 57
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#define CLK_DEINTERLACE 58
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#define CLK_TVE2_CLK 59
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#define CLK_TVE1_CLK 60
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#define CLK_TVD 61
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#define CLK_CSI 62
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#define CLK_VE 63
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#define CLK_CODEC 64
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#define CLK_AVS 65
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#endif
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