395 lines
11 KiB
C
395 lines
11 KiB
C
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/*
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* Marvell 88E6xxx Ethernet switch single-chip definition
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _MV88E6XXX_CHIP_H
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#define _MV88E6XXX_CHIP_H
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#include <linux/if_vlan.h>
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#include <linux/irq.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#ifndef UINT64_MAX
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#define UINT64_MAX (u64)(~((u64)0))
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#endif
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#define SMI_CMD 0x00
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#define SMI_CMD_BUSY BIT(15)
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#define SMI_CMD_CLAUSE_22 BIT(12)
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#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
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#define SMI_DATA 0x01
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#define MV88E6XXX_N_FID 4096
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/* PVT limits for 4-bit port and 5-bit switch */
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#define MV88E6XXX_MAX_PVT_SWITCHES 32
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#define MV88E6XXX_MAX_PVT_PORTS 16
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enum mv88e6xxx_egress_mode {
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MV88E6XXX_EGRESS_MODE_UNMODIFIED,
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MV88E6XXX_EGRESS_MODE_UNTAGGED,
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MV88E6XXX_EGRESS_MODE_TAGGED,
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MV88E6XXX_EGRESS_MODE_ETHERTYPE,
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};
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enum mv88e6xxx_frame_mode {
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MV88E6XXX_FRAME_MODE_NORMAL,
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MV88E6XXX_FRAME_MODE_DSA,
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MV88E6XXX_FRAME_MODE_PROVIDER,
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MV88E6XXX_FRAME_MODE_ETHERTYPE,
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};
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/* List of supported models */
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enum mv88e6xxx_model {
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MV88E6085,
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MV88E6095,
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MV88E6097,
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MV88E6123,
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MV88E6131,
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MV88E6141,
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MV88E6161,
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MV88E6165,
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MV88E6171,
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MV88E6172,
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MV88E6175,
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MV88E6176,
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MV88E6185,
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MV88E6190,
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MV88E6190X,
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MV88E6191,
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MV88E6240,
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MV88E6290,
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MV88E6320,
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MV88E6321,
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MV88E6341,
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MV88E6350,
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MV88E6351,
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MV88E6352,
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MV88E6390,
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MV88E6390X,
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};
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enum mv88e6xxx_family {
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MV88E6XXX_FAMILY_NONE,
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MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
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MV88E6XXX_FAMILY_6095, /* 6092 6095 */
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MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
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MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
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MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
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MV88E6XXX_FAMILY_6320, /* 6320 6321 */
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MV88E6XXX_FAMILY_6341, /* 6141 6341 */
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MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
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MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
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MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
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};
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struct mv88e6xxx_ops;
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struct mv88e6xxx_info {
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enum mv88e6xxx_family family;
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u16 prod_num;
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const char *name;
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unsigned int num_databases;
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unsigned int num_ports;
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unsigned int max_vid;
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unsigned int port_base_addr;
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unsigned int global1_addr;
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unsigned int global2_addr;
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unsigned int age_time_coeff;
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unsigned int g1_irqs;
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unsigned int g2_irqs;
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bool pvt;
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/* Multi-chip Addressing Mode.
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* Some chips respond to only 2 registers of its own SMI device address
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* when it is non-zero, and use indirect access to internal registers.
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*/
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bool multi_chip;
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enum dsa_tag_protocol tag_protocol;
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/* Mask for FromPort and ToPort value of PortVec used in ATU Move
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* operation. 0 means that the ATU Move operation is not supported.
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*/
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u8 atu_move_port_mask;
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const struct mv88e6xxx_ops *ops;
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};
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struct mv88e6xxx_atu_entry {
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u8 state;
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bool trunk;
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u16 portvec;
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u8 mac[ETH_ALEN];
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};
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struct mv88e6xxx_vtu_entry {
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u16 vid;
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u16 fid;
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u8 sid;
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bool valid;
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u8 member[DSA_MAX_PORTS];
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u8 state[DSA_MAX_PORTS];
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};
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struct mv88e6xxx_bus_ops;
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struct mv88e6xxx_irq_ops;
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struct mv88e6xxx_irq {
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u16 masked;
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struct irq_chip chip;
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struct irq_domain *domain;
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unsigned int nirqs;
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};
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struct mv88e6xxx_chip {
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const struct mv88e6xxx_info *info;
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/* The dsa_switch this private structure is related to */
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struct dsa_switch *ds;
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/* The device this structure is associated to */
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struct device *dev;
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/* This mutex protects the access to the switch registers */
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struct mutex reg_lock;
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/* The MII bus and the address on the bus that is used to
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* communication with the switch
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*/
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const struct mv88e6xxx_bus_ops *smi_ops;
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struct mii_bus *bus;
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int sw_addr;
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/* Handles automatic disabling and re-enabling of the PHY
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* polling unit.
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*/
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const struct mv88e6xxx_bus_ops *phy_ops;
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struct mutex ppu_mutex;
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int ppu_disabled;
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struct work_struct ppu_work;
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struct timer_list ppu_timer;
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/* This mutex serialises access to the statistics unit.
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* Hold this mutex over snapshot + dump sequences.
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*/
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struct mutex stats_mutex;
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/* A switch may have a GPIO line tied to its reset pin. Parse
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* this from the device tree, and use it before performing
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* switch soft reset.
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*/
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struct gpio_desc *reset;
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/* set to size of eeprom if supported by the switch */
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int eeprom_len;
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/* List of mdio busses */
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struct list_head mdios;
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/* There can be two interrupt controllers, which are chained
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* off a GPIO as interrupt source
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*/
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struct mv88e6xxx_irq g1_irq;
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struct mv88e6xxx_irq g2_irq;
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int irq;
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int device_irq;
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int watchdog_irq;
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};
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struct mv88e6xxx_bus_ops {
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int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
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int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
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};
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struct mv88e6xxx_mdio_bus {
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struct mii_bus *bus;
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struct mv88e6xxx_chip *chip;
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struct list_head list;
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bool external;
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};
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struct mv88e6xxx_ops {
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/* Ingress Rate Limit unit (IRL) operations */
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int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
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int (*get_eeprom)(struct mv88e6xxx_chip *chip,
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struct ethtool_eeprom *eeprom, u8 *data);
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int (*set_eeprom)(struct mv88e6xxx_chip *chip,
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struct ethtool_eeprom *eeprom, u8 *data);
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int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
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int (*phy_read)(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus,
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int addr, int reg, u16 *val);
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int (*phy_write)(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus,
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int addr, int reg, u16 val);
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/* Priority Override Table operations */
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int (*pot_clear)(struct mv88e6xxx_chip *chip);
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/* PHY Polling Unit (PPU) operations */
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int (*ppu_enable)(struct mv88e6xxx_chip *chip);
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int (*ppu_disable)(struct mv88e6xxx_chip *chip);
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/* Switch Software Reset */
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int (*reset)(struct mv88e6xxx_chip *chip);
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/* RGMII Receive/Transmit Timing Control
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* Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
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*/
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int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode);
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#define LINK_FORCED_DOWN 0
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#define LINK_FORCED_UP 1
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#define LINK_UNFORCED -2
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/* Port's MAC link state
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* Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
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* or LINK_UNFORCED for normal link detection.
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*/
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int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
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#define DUPLEX_UNFORCED -2
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/* Port's MAC duplex mode
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*
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* Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
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* or DUPLEX_UNFORCED for normal duplex detection.
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*/
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int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
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#define SPEED_MAX INT_MAX
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#define SPEED_UNFORCED -2
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/* Port's MAC speed (in Mbps)
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*
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* Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
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* Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
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*/
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int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
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int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
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int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_frame_mode mode);
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int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
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bool unicast, bool multicast);
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int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
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u16 etype);
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int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
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size_t size);
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int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
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int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
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u8 out);
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int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
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int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
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/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
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* Some chips allow this to be configured on specific ports.
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*/
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int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode);
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/* Some devices have a per port register indicating what is
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* the upstream port this port should forward to.
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*/
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int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
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int upstream_port);
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/* Snapshot the statistics for a port. The statistics can then
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* be read back a leisure but still with a consistent view.
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*/
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int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
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/* Set the histogram mode for statistics, when the control registers
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* are separated out of the STATS_OP register.
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*/
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int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
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/* Return the number of strings describing statistics */
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int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
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void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
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void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data);
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int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
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int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
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const struct mv88e6xxx_irq_ops *watchdog_ops;
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int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
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/* Power on/off a SERDES interface */
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int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
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/* VLAN Translation Unit operations */
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int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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};
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struct mv88e6xxx_irq_ops {
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/* Action to be performed when the interrupt happens */
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int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
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/* Setup the hardware to generate the interrupt */
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||
|
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int (*irq_setup)(struct mv88e6xxx_chip *chip);
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||
|
|
/* Reset the hardware to stop generating the interrupt */
|
||
|
|
void (*irq_free)(struct mv88e6xxx_chip *chip);
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||
|
|
};
|
||
|
|
|
||
|
|
#define STATS_TYPE_PORT BIT(0)
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||
|
|
#define STATS_TYPE_BANK0 BIT(1)
|
||
|
|
#define STATS_TYPE_BANK1 BIT(2)
|
||
|
|
|
||
|
|
struct mv88e6xxx_hw_stat {
|
||
|
|
char string[ETH_GSTRING_LEN];
|
||
|
|
int sizeof_stat;
|
||
|
|
int reg;
|
||
|
|
int type;
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
|
||
|
|
{
|
||
|
|
return chip->info->pvt;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
|
||
|
|
{
|
||
|
|
return chip->info->num_databases;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
|
||
|
|
{
|
||
|
|
return chip->info->num_ports;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
|
||
|
|
{
|
||
|
|
return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
|
||
|
|
int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
|
||
|
|
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
|
||
|
|
u16 update);
|
||
|
|
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
|
||
|
|
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
#endif /* _MV88E6XXX_CHIP_H */
|