340 lines
13 KiB
C
340 lines
13 KiB
C
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/*
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* Cobalt CPLD functions
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*
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* Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/delay.h>
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#include "cobalt-cpld.h"
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#define ADRS(offset) (COBALT_BUS_CPLD_BASE + offset)
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static u16 cpld_read(struct cobalt *cobalt, u32 offset)
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{
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return cobalt_bus_read32(cobalt->bar1, ADRS(offset));
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}
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static void cpld_write(struct cobalt *cobalt, u32 offset, u16 val)
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{
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return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val);
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}
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static void cpld_info_ver3(struct cobalt *cobalt)
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{
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u32 rd;
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u32 tmp;
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cobalt_info("CPLD System control register (read/write)\n");
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cobalt_info("\t\tSystem control: 0x%04x (0x0f00)\n",
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cpld_read(cobalt, 0));
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cobalt_info("CPLD Clock control register (read/write)\n");
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cobalt_info("\t\tClock control: 0x%04x (0x0000)\n",
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cpld_read(cobalt, 0x04));
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cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\n");
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cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n",
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cpld_read(cobalt, 0x08));
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cobalt_info("\t\tRegister #8:\t0x%04x (0x0047)\n",
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cpld_read(cobalt, 0x0c));
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cobalt_info("\t\tRegister #9:\t0x%04x (0x00fa)\n",
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cpld_read(cobalt, 0x10));
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cobalt_info("\t\tRegister #10:\t0x%04x (0x0061)\n",
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cpld_read(cobalt, 0x14));
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cobalt_info("\t\tRegister #11:\t0x%04x (0x001e)\n",
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cpld_read(cobalt, 0x18));
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cobalt_info("\t\tRegister #12:\t0x%04x (0x0045)\n",
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cpld_read(cobalt, 0x1c));
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cobalt_info("\t\tRegister #135:\t0x%04x\n",
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cpld_read(cobalt, 0x20));
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cobalt_info("\t\tRegister #137:\t0x%04x\n",
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cpld_read(cobalt, 0x24));
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cobalt_info("CPLD System status register (read only)\n");
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cobalt_info("\t\tSystem status: 0x%04x\n",
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cpld_read(cobalt, 0x28));
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cobalt_info("CPLD MAXII info register (read only)\n");
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cobalt_info("\t\tBoard serial number: 0x%04x\n",
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cpld_read(cobalt, 0x2c));
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cobalt_info("\t\tMAXII program revision: 0x%04x\n",
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cpld_read(cobalt, 0x30));
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cobalt_info("CPLD temp and voltage ADT7411 registers (read only)\n");
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cobalt_info("\t\tBoard temperature: %u Celsius\n",
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cpld_read(cobalt, 0x34) / 4);
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cobalt_info("\t\tFPGA temperature: %u Celsius\n",
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cpld_read(cobalt, 0x38) / 4);
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rd = cpld_read(cobalt, 0x3c);
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tmp = (rd * 33 * 1000) / (483 * 10);
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cobalt_info("\t\tVDD 3V3: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x40);
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tmp = (rd * 74 * 2197) / (27 * 1000);
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cobalt_info("\t\tADC ch3 5V: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x44);
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tmp = (rd * 74 * 2197) / (47 * 1000);
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cobalt_info("\t\tADC ch4 3V: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x48);
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tmp = (rd * 57 * 2197) / (47 * 1000);
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cobalt_info("\t\tADC ch5 2V5: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x4c);
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tmp = (rd * 2197) / 1000;
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cobalt_info("\t\tADC ch6 1V8: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x50);
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tmp = (rd * 2197) / 1000;
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cobalt_info("\t\tADC ch7 1V5: %u,%03uV\n", tmp / 1000, tmp % 1000);
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rd = cpld_read(cobalt, 0x54);
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tmp = (rd * 2197) / 1000;
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cobalt_info("\t\tADC ch8 0V9: %u,%03uV\n", tmp / 1000, tmp % 1000);
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}
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void cobalt_cpld_status(struct cobalt *cobalt)
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{
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u32 rev = cpld_read(cobalt, 0x30);
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switch (rev) {
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case 3:
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case 4:
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case 5:
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cpld_info_ver3(cobalt);
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break;
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default:
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cobalt_info("CPLD revision %u is not supported!\n", rev);
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break;
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}
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}
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#define DCO_MIN 4850000000ULL
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#define DCO_MAX 5670000000ULL
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#define SI570_CLOCK_CTRL 0x04
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#define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_WR_TRIGGER 0x200
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#define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_RST_TRIGGER 0x100
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#define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL 0x80
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#define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN 0x40
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#define SI570_REG7 0x08
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#define SI570_REG8 0x0c
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#define SI570_REG9 0x10
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#define SI570_REG10 0x14
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#define SI570_REG11 0x18
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#define SI570_REG12 0x1c
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#define SI570_REG135 0x20
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#define SI570_REG137 0x24
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struct multiplier {
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unsigned mult, hsdiv, n1;
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};
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/* List all possible multipliers (= hsdiv * n1). There are lots of duplicates,
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which are all removed in this list to keep the list as short as possible.
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The values for hsdiv and n1 are the actual values, not the register values.
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*/
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static const struct multiplier multipliers[] = {
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{ 4, 4, 1 }, { 5, 5, 1 }, { 6, 6, 1 },
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{ 7, 7, 1 }, { 8, 4, 2 }, { 9, 9, 1 },
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{ 10, 5, 2 }, { 11, 11, 1 }, { 12, 6, 2 },
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{ 14, 7, 2 }, { 16, 4, 4 }, { 18, 9, 2 },
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{ 20, 5, 4 }, { 22, 11, 2 }, { 24, 4, 6 },
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{ 28, 7, 4 }, { 30, 5, 6 }, { 32, 4, 8 },
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{ 36, 6, 6 }, { 40, 4, 10 }, { 42, 7, 6 },
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{ 44, 11, 4 }, { 48, 4, 12 }, { 50, 5, 10 },
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{ 54, 9, 6 }, { 56, 4, 14 }, { 60, 5, 12 },
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{ 64, 4, 16 }, { 66, 11, 6 }, { 70, 5, 14 },
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{ 72, 4, 18 }, { 80, 4, 20 }, { 84, 6, 14 },
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{ 88, 11, 8 }, { 90, 5, 18 }, { 96, 4, 24 },
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{ 98, 7, 14 }, { 100, 5, 20 }, { 104, 4, 26 },
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{ 108, 6, 18 }, { 110, 11, 10 }, { 112, 4, 28 },
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{ 120, 4, 30 }, { 126, 7, 18 }, { 128, 4, 32 },
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{ 130, 5, 26 }, { 132, 11, 12 }, { 136, 4, 34 },
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{ 140, 5, 28 }, { 144, 4, 36 }, { 150, 5, 30 },
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{ 152, 4, 38 }, { 154, 11, 14 }, { 156, 6, 26 },
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{ 160, 4, 40 }, { 162, 9, 18 }, { 168, 4, 42 },
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{ 170, 5, 34 }, { 176, 11, 16 }, { 180, 5, 36 },
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{ 182, 7, 26 }, { 184, 4, 46 }, { 190, 5, 38 },
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{ 192, 4, 48 }, { 196, 7, 28 }, { 198, 11, 18 },
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{ 198, 9, 22 }, { 200, 4, 50 }, { 204, 6, 34 },
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{ 208, 4, 52 }, { 210, 5, 42 }, { 216, 4, 54 },
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{ 220, 11, 20 }, { 224, 4, 56 }, { 228, 6, 38 },
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{ 230, 5, 46 }, { 232, 4, 58 }, { 234, 9, 26 },
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{ 238, 7, 34 }, { 240, 4, 60 }, { 242, 11, 22 },
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{ 248, 4, 62 }, { 250, 5, 50 }, { 252, 6, 42 },
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{ 256, 4, 64 }, { 260, 5, 52 }, { 264, 11, 24 },
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{ 266, 7, 38 }, { 270, 5, 54 }, { 272, 4, 68 },
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{ 276, 6, 46 }, { 280, 4, 70 }, { 286, 11, 26 },
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{ 288, 4, 72 }, { 290, 5, 58 }, { 294, 7, 42 },
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{ 296, 4, 74 }, { 300, 5, 60 }, { 304, 4, 76 },
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{ 306, 9, 34 }, { 308, 11, 28 }, { 310, 5, 62 },
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{ 312, 4, 78 }, { 320, 4, 80 }, { 322, 7, 46 },
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{ 324, 6, 54 }, { 328, 4, 82 }, { 330, 11, 30 },
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{ 336, 4, 84 }, { 340, 5, 68 }, { 342, 9, 38 },
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{ 344, 4, 86 }, { 348, 6, 58 }, { 350, 5, 70 },
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{ 352, 11, 32 }, { 360, 4, 90 }, { 364, 7, 52 },
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{ 368, 4, 92 }, { 370, 5, 74 }, { 372, 6, 62 },
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{ 374, 11, 34 }, { 376, 4, 94 }, { 378, 7, 54 },
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{ 380, 5, 76 }, { 384, 4, 96 }, { 390, 5, 78 },
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{ 392, 4, 98 }, { 396, 11, 36 }, { 400, 4, 100 },
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{ 406, 7, 58 }, { 408, 4, 102 }, { 410, 5, 82 },
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{ 414, 9, 46 }, { 416, 4, 104 }, { 418, 11, 38 },
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{ 420, 5, 84 }, { 424, 4, 106 }, { 430, 5, 86 },
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{ 432, 4, 108 }, { 434, 7, 62 }, { 440, 11, 40 },
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{ 444, 6, 74 }, { 448, 4, 112 }, { 450, 5, 90 },
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{ 456, 4, 114 }, { 460, 5, 92 }, { 462, 11, 42 },
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{ 464, 4, 116 }, { 468, 6, 78 }, { 470, 5, 94 },
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{ 472, 4, 118 }, { 476, 7, 68 }, { 480, 4, 120 },
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{ 484, 11, 44 }, { 486, 9, 54 }, { 488, 4, 122 },
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{ 490, 5, 98 }, { 492, 6, 82 }, { 496, 4, 124 },
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{ 500, 5, 100 }, { 504, 4, 126 }, { 506, 11, 46 },
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{ 510, 5, 102 }, { 512, 4, 128 }, { 516, 6, 86 },
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{ 518, 7, 74 }, { 520, 5, 104 }, { 522, 9, 58 },
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{ 528, 11, 48 }, { 530, 5, 106 }, { 532, 7, 76 },
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{ 540, 5, 108 }, { 546, 7, 78 }, { 550, 11, 50 },
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{ 552, 6, 92 }, { 558, 9, 62 }, { 560, 5, 112 },
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{ 564, 6, 94 }, { 570, 5, 114 }, { 572, 11, 52 },
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{ 574, 7, 82 }, { 576, 6, 96 }, { 580, 5, 116 },
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{ 588, 6, 98 }, { 590, 5, 118 }, { 594, 11, 54 },
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{ 600, 5, 120 }, { 602, 7, 86 }, { 610, 5, 122 },
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{ 612, 6, 102 }, { 616, 11, 56 }, { 620, 5, 124 },
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{ 624, 6, 104 }, { 630, 5, 126 }, { 636, 6, 106 },
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{ 638, 11, 58 }, { 640, 5, 128 }, { 644, 7, 92 },
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{ 648, 6, 108 }, { 658, 7, 94 }, { 660, 11, 60 },
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{ 666, 9, 74 }, { 672, 6, 112 }, { 682, 11, 62 },
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{ 684, 6, 114 }, { 686, 7, 98 }, { 696, 6, 116 },
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{ 700, 7, 100 }, { 702, 9, 78 }, { 704, 11, 64 },
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{ 708, 6, 118 }, { 714, 7, 102 }, { 720, 6, 120 },
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{ 726, 11, 66 }, { 728, 7, 104 }, { 732, 6, 122 },
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{ 738, 9, 82 }, { 742, 7, 106 }, { 744, 6, 124 },
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{ 748, 11, 68 }, { 756, 6, 126 }, { 768, 6, 128 },
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{ 770, 11, 70 }, { 774, 9, 86 }, { 784, 7, 112 },
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{ 792, 11, 72 }, { 798, 7, 114 }, { 810, 9, 90 },
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{ 812, 7, 116 }, { 814, 11, 74 }, { 826, 7, 118 },
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{ 828, 9, 92 }, { 836, 11, 76 }, { 840, 7, 120 },
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{ 846, 9, 94 }, { 854, 7, 122 }, { 858, 11, 78 },
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{ 864, 9, 96 }, { 868, 7, 124 }, { 880, 11, 80 },
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{ 882, 7, 126 }, { 896, 7, 128 }, { 900, 9, 100 },
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{ 902, 11, 82 }, { 918, 9, 102 }, { 924, 11, 84 },
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{ 936, 9, 104 }, { 946, 11, 86 }, { 954, 9, 106 },
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{ 968, 11, 88 }, { 972, 9, 108 }, { 990, 11, 90 },
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{ 1008, 9, 112 }, { 1012, 11, 92 }, { 1026, 9, 114 },
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{ 1034, 11, 94 }, { 1044, 9, 116 }, { 1056, 11, 96 },
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{ 1062, 9, 118 }, { 1078, 11, 98 }, { 1080, 9, 120 },
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{ 1098, 9, 122 }, { 1100, 11, 100 }, { 1116, 9, 124 },
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{ 1122, 11, 102 }, { 1134, 9, 126 }, { 1144, 11, 104 },
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{ 1152, 9, 128 }, { 1166, 11, 106 }, { 1188, 11, 108 },
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{ 1210, 11, 110 }, { 1232, 11, 112 }, { 1254, 11, 114 },
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{ 1276, 11, 116 }, { 1298, 11, 118 }, { 1320, 11, 120 },
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{ 1342, 11, 122 }, { 1364, 11, 124 }, { 1386, 11, 126 },
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{ 1408, 11, 128 },
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};
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bool cobalt_cpld_set_freq(struct cobalt *cobalt, unsigned f_out)
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{
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const unsigned f_xtal = 39170000; /* xtal for si598 */
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u64 dco;
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u64 rfreq;
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unsigned delta = 0xffffffff;
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unsigned i_best = 0;
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unsigned i;
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u8 n1, hsdiv;
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u8 regs[6];
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int found = 0;
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u16 clock_ctrl;
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int retries = 3;
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for (i = 0; i < ARRAY_SIZE(multipliers); i++) {
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unsigned mult = multipliers[i].mult;
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u32 d;
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dco = (u64)f_out * mult;
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if (dco < DCO_MIN || dco > DCO_MAX)
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continue;
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div_u64_rem((dco << 28) + f_xtal / 2, f_xtal, &d);
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if (d < delta) {
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found = 1;
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i_best = i;
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delta = d;
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}
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}
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if (!found)
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return false;
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dco = (u64)f_out * multipliers[i_best].mult;
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n1 = multipliers[i_best].n1 - 1;
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hsdiv = multipliers[i_best].hsdiv - 4;
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rfreq = div_u64(dco << 28, f_xtal);
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clock_ctrl = cpld_read(cobalt, SI570_CLOCK_CTRL);
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clock_ctrl |= S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL;
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clock_ctrl |= S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN;
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regs[0] = (hsdiv << 5) | (n1 >> 2);
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regs[1] = ((n1 & 0x3) << 6) | (rfreq >> 32);
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regs[2] = (rfreq >> 24) & 0xff;
|
||
|
|
regs[3] = (rfreq >> 16) & 0xff;
|
||
|
|
regs[4] = (rfreq >> 8) & 0xff;
|
||
|
|
regs[5] = rfreq & 0xff;
|
||
|
|
|
||
|
|
/* The sequence of clock_ctrl flags to set is very weird. It looks
|
||
|
|
like I have to reset it, then set the new frequency and reset it
|
||
|
|
again. It shouldn't be necessary to do a reset, but if I don't,
|
||
|
|
then a strange frequency is set (156.412034 MHz, or register values
|
||
|
|
0x01, 0xc7, 0xfc, 0x7f, 0x53, 0x62).
|
||
|
|
*/
|
||
|
|
|
||
|
|
cobalt_dbg(1, "%u: %6ph\n", f_out, regs);
|
||
|
|
|
||
|
|
while (retries--) {
|
||
|
|
u8 read_regs[6];
|
||
|
|
|
||
|
|
cpld_write(cobalt, SI570_CLOCK_CTRL,
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN |
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL);
|
||
|
|
usleep_range(10000, 15000);
|
||
|
|
cpld_write(cobalt, SI570_REG7, regs[0]);
|
||
|
|
cpld_write(cobalt, SI570_REG8, regs[1]);
|
||
|
|
cpld_write(cobalt, SI570_REG9, regs[2]);
|
||
|
|
cpld_write(cobalt, SI570_REG10, regs[3]);
|
||
|
|
cpld_write(cobalt, SI570_REG11, regs[4]);
|
||
|
|
cpld_write(cobalt, SI570_REG12, regs[5]);
|
||
|
|
cpld_write(cobalt, SI570_CLOCK_CTRL,
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN |
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_WR_TRIGGER);
|
||
|
|
usleep_range(10000, 15000);
|
||
|
|
cpld_write(cobalt, SI570_CLOCK_CTRL,
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN |
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL);
|
||
|
|
usleep_range(10000, 15000);
|
||
|
|
read_regs[0] = cpld_read(cobalt, SI570_REG7);
|
||
|
|
read_regs[1] = cpld_read(cobalt, SI570_REG8);
|
||
|
|
read_regs[2] = cpld_read(cobalt, SI570_REG9);
|
||
|
|
read_regs[3] = cpld_read(cobalt, SI570_REG10);
|
||
|
|
read_regs[4] = cpld_read(cobalt, SI570_REG11);
|
||
|
|
read_regs[5] = cpld_read(cobalt, SI570_REG12);
|
||
|
|
cpld_write(cobalt, SI570_CLOCK_CTRL,
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN |
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL |
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_RST_TRIGGER);
|
||
|
|
usleep_range(10000, 15000);
|
||
|
|
cpld_write(cobalt, SI570_CLOCK_CTRL,
|
||
|
|
S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN);
|
||
|
|
usleep_range(10000, 15000);
|
||
|
|
|
||
|
|
if (!memcmp(read_regs, regs, sizeof(read_regs)))
|
||
|
|
break;
|
||
|
|
cobalt_dbg(1, "retry: %6ph\n", read_regs);
|
||
|
|
}
|
||
|
|
if (2 - retries)
|
||
|
|
cobalt_info("Needed %d retries\n", 2 - retries);
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|