331 lines
13 KiB
C
331 lines
13 KiB
C
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#ifndef _PIO_H
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#define _PIO_H
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/*
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* Copyright(c) 2015-2017 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* send context types */
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#define SC_KERNEL 0
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#define SC_VL15 1
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#define SC_ACK 2
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#define SC_USER 3 /* must be the last one: it may take all left */
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#define SC_MAX 4 /* count of send context types */
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/* invalid send context index */
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#define INVALID_SCI 0xff
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/* PIO buffer release callback function */
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typedef void (*pio_release_cb)(void *arg, int code);
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/* PIO release codes - in bits, as there could more than one that apply */
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#define PRC_OK 0 /* no known error */
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#define PRC_STATUS_ERR 0x01 /* credit return due to status error */
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#define PRC_PBC 0x02 /* credit return due to PBC */
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#define PRC_THRESHOLD 0x04 /* credit return due to threshold */
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#define PRC_FILL_ERR 0x08 /* credit return due fill error */
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#define PRC_FORCE 0x10 /* credit return due credit force */
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#define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */
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/* byte helper */
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union mix {
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u64 val64;
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u32 val32[2];
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u8 val8[8];
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};
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/* an allocated PIO buffer */
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struct pio_buf {
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struct send_context *sc;/* back pointer to owning send context */
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pio_release_cb cb; /* called when the buffer is released */
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void *arg; /* argument for cb */
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void __iomem *start; /* buffer start address */
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void __iomem *end; /* context end address */
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unsigned long sent_at; /* buffer is sent when <= free */
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union mix carry; /* pending unwritten bytes */
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u16 qw_written; /* QW written so far */
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u8 carry_bytes; /* number of valid bytes in carry */
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};
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/* cache line aligned pio buffer array */
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union pio_shadow_ring {
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struct pio_buf pbuf;
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} ____cacheline_aligned;
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/* per-NUMA send context */
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struct send_context {
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/* read-only after init */
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struct hfi1_devdata *dd; /* device */
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union pio_shadow_ring *sr; /* shadow ring */
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void __iomem *base_addr; /* start of PIO memory */
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u32 __percpu *buffers_allocated;/* count of buffers allocated */
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u32 size; /* context size, in bytes */
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int node; /* context home node */
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u32 sr_size; /* size of the shadow ring */
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u16 flags; /* flags */
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u8 type; /* context type */
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u8 sw_index; /* software index number */
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u8 hw_context; /* hardware context number */
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u8 group; /* credit return group */
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/* allocator fields */
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spinlock_t alloc_lock ____cacheline_aligned_in_smp;
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u32 sr_head; /* shadow ring head */
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unsigned long fill; /* official alloc count */
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unsigned long alloc_free; /* copy of free (less cache thrash) */
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u32 fill_wrap; /* tracks fill within ring */
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u32 credits; /* number of blocks in context */
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/* adding a new field here would make it part of this cacheline */
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/* releaser fields */
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spinlock_t release_lock ____cacheline_aligned_in_smp;
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u32 sr_tail; /* shadow ring tail */
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unsigned long free; /* official free count */
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volatile __le64 *hw_free; /* HW free counter */
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/* list for PIO waiters */
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struct list_head piowait ____cacheline_aligned_in_smp;
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spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
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u32 credit_intr_count; /* count of credit intr users */
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u64 credit_ctrl; /* cache for credit control */
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wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */
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struct work_struct halt_work; /* halted context work queue entry */
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};
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/* send context flags */
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#define SCF_ENABLED 0x01
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#define SCF_IN_FREE 0x02
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#define SCF_HALTED 0x04
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#define SCF_FROZEN 0x08
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struct send_context_info {
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struct send_context *sc; /* allocated working context */
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u16 allocated; /* has this been allocated? */
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u16 type; /* context type */
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u16 base; /* base in PIO array */
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u16 credits; /* size in PIO array */
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};
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/* DMA credit return, index is always (context & 0x7) */
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struct credit_return {
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volatile __le64 cr[8];
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};
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/* NUMA indexed credit return array */
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struct credit_return_base {
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struct credit_return *va;
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dma_addr_t dma;
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};
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/* send context configuration sizes (one per type) */
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struct sc_config_sizes {
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short int size;
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short int count;
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};
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/*
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* The diagram below details the relationship of the mapping structures
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*
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* Since the mapping now allows for non-uniform send contexts per vl, the
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* number of send contexts for a vl is either the vl_scontexts[vl] or
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* a computation based on num_kernel_send_contexts/num_vls:
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*
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* For example:
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* nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
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*
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* n = roundup to next highest power of 2 using nactual
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*
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* In the case where there are num_kernel_send_contexts/num_vls doesn't divide
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* evenly, the extras are added from the last vl downward.
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*
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* For the case where n > nactual, the send contexts are assigned
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* in a round robin fashion wrapping back to the first send context
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* for a particular vl.
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*
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* dd->pio_map
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* | pio_map_elem[0]
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* | +--------------------+
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* v | mask |
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* pio_vl_map |--------------------|
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* +--------------------------+ | ksc[0] -> sc 1 |
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* | list (RCU) | |--------------------|
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* |--------------------------| ->| ksc[1] -> sc 2 |
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* | mask | --/ |--------------------|
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* |--------------------------| -/ | * |
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* | actual_vls (max 8) | -/ |--------------------|
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* |--------------------------| --/ | ksc[n-1] -> sc n |
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* | vls (max 8) | -/ +--------------------+
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* |--------------------------| --/
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* | map[0] |-/
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* |--------------------------| +--------------------+
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* | map[1] |--- | mask |
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* |--------------------------| \---- |--------------------|
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* | * | \-- | ksc[0] -> sc 1+n |
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* | * | \---- |--------------------|
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* | * | \->| ksc[1] -> sc 2+n |
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* |--------------------------| |--------------------|
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* | map[vls - 1] |- | * |
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* +--------------------------+ \- |--------------------|
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* \- | ksc[m-1] -> sc m+n |
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* \ +--------------------+
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* \-
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* \
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* \- +----------------------+
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* \- | mask |
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* \ |----------------------|
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* \- | ksc[0] -> sc 1+m+n |
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* \- |----------------------|
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* >| ksc[1] -> sc 2+m+n |
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* |----------------------|
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* | * |
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* |----------------------|
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* | ksc[o-1] -> sc o+m+n |
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* +----------------------+
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*
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*/
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/* Initial number of send contexts per VL */
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#define INIT_SC_PER_VL 2
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/*
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* struct pio_map_elem - mapping for a vl
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* @mask - selector mask
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* @ksc - array of kernel send contexts for this vl
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*
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* The mask is used to "mod" the selector to
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* produce index into the trailing array of
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* kscs
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*/
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struct pio_map_elem {
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u32 mask;
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struct send_context *ksc[0];
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};
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/*
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* struct pio_vl_map - mapping for a vl
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* @list - rcu head for free callback
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* @mask - vl mask to "mod" the vl to produce an index to map array
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* @actual_vls - number of vls
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* @vls - numbers of vls rounded to next power of 2
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* @map - array of pio_map_elem entries
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*
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* This is the parent mapping structure. The trailing members of the
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* struct point to pio_map_elem entries, which in turn point to an
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* array of kscs for that vl.
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*/
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struct pio_vl_map {
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struct rcu_head list;
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u32 mask;
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u8 actual_vls;
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u8 vls;
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struct pio_map_elem *map[0];
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};
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int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
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u8 *vl_scontexts);
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void free_pio_map(struct hfi1_devdata *dd);
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struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
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u32 selector, u8 vl);
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struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
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u32 selector, u8 sc5);
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/* send context functions */
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int init_credit_return(struct hfi1_devdata *dd);
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void free_credit_return(struct hfi1_devdata *dd);
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int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
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int init_send_contexts(struct hfi1_devdata *dd);
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int init_credit_return(struct hfi1_devdata *dd);
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int init_pervl_scs(struct hfi1_devdata *dd);
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struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
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uint hdrqentsize, int numa);
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void sc_free(struct send_context *sc);
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int sc_enable(struct send_context *sc);
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void sc_disable(struct send_context *sc);
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int sc_restart(struct send_context *sc);
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void sc_return_credits(struct send_context *sc);
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void sc_flush(struct send_context *sc);
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void sc_drop(struct send_context *sc);
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void sc_stop(struct send_context *sc, int bit);
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struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
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pio_release_cb cb, void *arg);
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void sc_release_update(struct send_context *sc);
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void sc_return_credits(struct send_context *sc);
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void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
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void sc_add_credit_return_intr(struct send_context *sc);
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void sc_del_credit_return_intr(struct send_context *sc);
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void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
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u32 sc_percent_to_threshold(struct send_context *sc, u32 percent);
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u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
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void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
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void sc_wait(struct hfi1_devdata *dd);
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void set_pio_integrity(struct send_context *sc);
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/* support functions */
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void pio_reset_all(struct hfi1_devdata *dd);
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void pio_freeze(struct hfi1_devdata *dd);
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void pio_kernel_unfreeze(struct hfi1_devdata *dd);
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/* global PIO send control operations */
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#define PSC_GLOBAL_ENABLE 0
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#define PSC_GLOBAL_DISABLE 1
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#define PSC_GLOBAL_VLARB_ENABLE 2
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#define PSC_GLOBAL_VLARB_DISABLE 3
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#define PSC_CM_RESET 4
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#define PSC_DATA_VL_ENABLE 5
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#define PSC_DATA_VL_DISABLE 6
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void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
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void pio_send_control(struct hfi1_devdata *dd, int op);
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/* PIO copy routines */
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void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
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const void *from, size_t count);
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void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
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const void *from, size_t nbytes);
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void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
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void seg_pio_copy_end(struct pio_buf *pbuf);
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#endif /* _PIO_H */
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