417 lines
12 KiB
C
417 lines
12 KiB
C
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "rv740d.h"
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#include "r600_dpm.h"
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#include "rv770_dpm.h"
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#include "atom.h"
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struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
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u32 rv740_get_decoded_reference_divider(u32 encoded_ref)
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{
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u32 ref = 0;
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switch (encoded_ref) {
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case 0:
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ref = 1;
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break;
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case 16:
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ref = 2;
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break;
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case 17:
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ref = 3;
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break;
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case 18:
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ref = 2;
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break;
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case 19:
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ref = 3;
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break;
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case 20:
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ref = 4;
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break;
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case 21:
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ref = 5;
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break;
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default:
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DRM_ERROR("Invalid encoded Reference Divider\n");
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ref = 0;
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break;
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}
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return ref;
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}
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struct dll_speed_setting {
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u16 min;
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u16 max;
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u32 dll_speed;
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};
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static struct dll_speed_setting dll_speed_table[16] =
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{
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{ 270, 320, 0x0f },
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{ 240, 270, 0x0e },
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{ 200, 240, 0x0d },
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{ 180, 200, 0x0c },
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{ 160, 180, 0x0b },
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{ 140, 160, 0x0a },
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{ 120, 140, 0x09 },
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{ 110, 120, 0x08 },
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{ 95, 110, 0x07 },
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{ 85, 95, 0x06 },
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{ 78, 85, 0x05 },
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{ 70, 78, 0x04 },
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{ 65, 70, 0x03 },
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{ 60, 65, 0x02 },
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{ 42, 60, 0x01 },
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{ 00, 42, 0x00 }
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};
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u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)
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{
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int i;
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u32 factor;
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u16 data_rate;
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if (is_gddr5)
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factor = 4;
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else
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factor = 2;
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data_rate = (u16)(memory_clock * factor / 1000);
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if (data_rate < dll_speed_table[0].max) {
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for (i = 0; i < 16; i++) {
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if (data_rate > dll_speed_table[i].min &&
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data_rate <= dll_speed_table[i].max)
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return dll_speed_table[i].dll_speed;
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}
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}
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DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n");
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return 0x0f;
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}
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int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
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RV770_SMC_SCLK_VALUE *sclk)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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struct atom_clock_dividers dividers;
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u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
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u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
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u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
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u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
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u64 tmp;
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u32 reference_clock = rdev->clock.spll.reference_freq;
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u32 reference_divider;
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u32 fbdiv;
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int ret;
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
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engine_clock, false, ÷rs);
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if (ret)
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return ret;
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reference_divider = 1 + dividers.ref_div;
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tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
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do_div(tmp, reference_clock);
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fbdiv = (u32) tmp;
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spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
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spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
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spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
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spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
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spll_func_cntl_2 |= SCLK_MUX_SEL(2);
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spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
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spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
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spll_func_cntl_3 |= SPLL_DITHEN;
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if (pi->sclk_ss) {
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struct radeon_atom_ss ss;
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u32 vco_freq = engine_clock * dividers.post_div;
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if (radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
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u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
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u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
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cg_spll_spread_spectrum &= ~CLK_S_MASK;
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cg_spll_spread_spectrum |= CLK_S(clk_s);
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cg_spll_spread_spectrum |= SSEN;
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cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
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cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
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}
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}
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sclk->sclk_value = cpu_to_be32(engine_clock);
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sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
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sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
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sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
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sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
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sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
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return 0;
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}
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int rv740_populate_mclk_value(struct radeon_device *rdev,
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u32 engine_clock, u32 memory_clock,
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RV7XX_SMC_MCLK_VALUE *mclk)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;
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u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;
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u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;
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u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;
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u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;
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u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
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u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
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u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
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struct atom_clock_dividers dividers;
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u32 ibias;
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u32 dll_speed;
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int ret;
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
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memory_clock, false, ÷rs);
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if (ret)
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return ret;
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ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
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mpll_ad_func_cntl &= ~(CLKR_MASK |
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YCLK_POST_DIV_MASK |
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CLKF_MASK |
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CLKFRAC_MASK |
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IBIAS_MASK);
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mpll_ad_func_cntl |= CLKR(dividers.ref_div);
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mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
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mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
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mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
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mpll_ad_func_cntl |= IBIAS(ibias);
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if (dividers.vco_mode)
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mpll_ad_func_cntl_2 |= VCO_MODE;
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else
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mpll_ad_func_cntl_2 &= ~VCO_MODE;
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if (pi->mem_gddr5) {
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mpll_dq_func_cntl &= ~(CLKR_MASK |
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YCLK_POST_DIV_MASK |
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CLKF_MASK |
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CLKFRAC_MASK |
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IBIAS_MASK);
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mpll_dq_func_cntl |= CLKR(dividers.ref_div);
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mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
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mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
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mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
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mpll_dq_func_cntl |= IBIAS(ibias);
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if (dividers.vco_mode)
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mpll_dq_func_cntl_2 |= VCO_MODE;
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else
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mpll_dq_func_cntl_2 &= ~VCO_MODE;
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}
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if (pi->mclk_ss) {
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struct radeon_atom_ss ss;
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u32 vco_freq = memory_clock * dividers.post_div;
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if (radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
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u32 reference_clock = rdev->clock.mpll.reference_freq;
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u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
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u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
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u32 clk_v = 0x40000 * ss.percentage *
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(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
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mpll_ss1 &= ~CLKV_MASK;
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mpll_ss1 |= CLKV(clk_v);
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mpll_ss2 &= ~CLKS_MASK;
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mpll_ss2 |= CLKS(clk_s);
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}
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}
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dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
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memory_clock);
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mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
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mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
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mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
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mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
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mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
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mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
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mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
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mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
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mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
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mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
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mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
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return 0;
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}
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void rv740_read_clock_registers(struct radeon_device *rdev)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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pi->clk_regs.rv770.cg_spll_func_cntl =
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RREG32(CG_SPLL_FUNC_CNTL);
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pi->clk_regs.rv770.cg_spll_func_cntl_2 =
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RREG32(CG_SPLL_FUNC_CNTL_2);
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pi->clk_regs.rv770.cg_spll_func_cntl_3 =
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RREG32(CG_SPLL_FUNC_CNTL_3);
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pi->clk_regs.rv770.cg_spll_spread_spectrum =
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RREG32(CG_SPLL_SPREAD_SPECTRUM);
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pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =
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RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
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pi->clk_regs.rv770.mpll_ad_func_cntl =
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RREG32(MPLL_AD_FUNC_CNTL);
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pi->clk_regs.rv770.mpll_ad_func_cntl_2 =
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RREG32(MPLL_AD_FUNC_CNTL_2);
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pi->clk_regs.rv770.mpll_dq_func_cntl =
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RREG32(MPLL_DQ_FUNC_CNTL);
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pi->clk_regs.rv770.mpll_dq_func_cntl_2 =
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RREG32(MPLL_DQ_FUNC_CNTL_2);
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pi->clk_regs.rv770.mclk_pwrmgt_cntl =
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RREG32(MCLK_PWRMGT_CNTL);
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pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
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pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
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pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);
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}
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int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
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RV770_SMC_STATETABLE *table)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;
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u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;
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||
|
|
u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;
|
||
|
|
u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;
|
||
|
|
u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
|
||
|
|
u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
|
||
|
|
u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
|
||
|
|
u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;
|
||
|
|
u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
|
||
|
|
|
||
|
|
table->ACPIState = table->initialState;
|
||
|
|
|
||
|
|
table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
|
||
|
|
|
||
|
|
if (pi->acpi_vddc) {
|
||
|
|
rv770_populate_vddc_value(rdev, pi->acpi_vddc,
|
||
|
|
&table->ACPIState.levels[0].vddc);
|
||
|
|
table->ACPIState.levels[0].gen2PCIE =
|
||
|
|
pi->pcie_gen2 ?
|
||
|
|
pi->acpi_pcie_gen2 : 0;
|
||
|
|
table->ACPIState.levels[0].gen2XSP =
|
||
|
|
pi->acpi_pcie_gen2;
|
||
|
|
} else {
|
||
|
|
rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
|
||
|
|
&table->ACPIState.levels[0].vddc);
|
||
|
|
table->ACPIState.levels[0].gen2PCIE = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
|
||
|
|
|
||
|
|
mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN;
|
||
|
|
|
||
|
|
mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
|
||
|
|
MRDCKA1_RESET |
|
||
|
|
MRDCKB0_RESET |
|
||
|
|
MRDCKB1_RESET |
|
||
|
|
MRDCKC0_RESET |
|
||
|
|
MRDCKC1_RESET |
|
||
|
|
MRDCKD0_RESET |
|
||
|
|
MRDCKD1_RESET);
|
||
|
|
|
||
|
|
dll_cntl |= (MRDCKA0_BYPASS |
|
||
|
|
MRDCKA1_BYPASS |
|
||
|
|
MRDCKB0_BYPASS |
|
||
|
|
MRDCKB1_BYPASS |
|
||
|
|
MRDCKC0_BYPASS |
|
||
|
|
MRDCKC1_BYPASS |
|
||
|
|
MRDCKD0_BYPASS |
|
||
|
|
MRDCKD1_BYPASS);
|
||
|
|
|
||
|
|
spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
|
||
|
|
|
||
|
|
spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
|
||
|
|
spll_func_cntl_2 |= SCLK_MUX_SEL(4);
|
||
|
|
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
|
||
|
|
|
||
|
|
table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
|
||
|
|
|
||
|
|
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
|
||
|
|
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
|
||
|
|
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
|
||
|
|
|
||
|
|
table->ACPIState.levels[0].sclk.sclk_value = 0;
|
||
|
|
|
||
|
|
table->ACPIState.levels[1] = table->ACPIState.levels[0];
|
||
|
|
table->ACPIState.levels[2] = table->ACPIState.levels[0];
|
||
|
|
|
||
|
|
rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
|
||
|
|
bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
|
||
|
|
else
|
||
|
|
WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)
|
||
|
|
{
|
||
|
|
u8 mc_para_index;
|
||
|
|
|
||
|
|
if ((memory_clock < 10000) || (memory_clock > 47500))
|
||
|
|
mc_para_index = 0x00;
|
||
|
|
else
|
||
|
|
mc_para_index = (u8)((memory_clock - 10000) / 2500);
|
||
|
|
|
||
|
|
return mc_para_index;
|
||
|
|
}
|