263 lines
7.7 KiB
C
263 lines
7.7 KiB
C
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr.h"
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#include "gm200.h"
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <engine/falcon.h>
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#include <subdev/mc.h>
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/**
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* gm200_secboot_run_blob() - run the given high-secure blob
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*
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*/
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int
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gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob,
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struct nvkm_falcon *falcon)
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{
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struct gm200_secboot *gsb = gm200_secboot(sb);
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struct nvkm_subdev *subdev = &gsb->base.subdev;
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struct nvkm_vma *vma = NULL;
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u32 start_address;
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int ret;
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ret = nvkm_falcon_get(falcon, subdev);
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if (ret)
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return ret;
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/* Map the HS firmware so the HS bootloader can see it */
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ret = nvkm_vmm_get(gsb->vmm, 12, blob->size, &vma);
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if (ret) {
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nvkm_falcon_put(falcon, subdev);
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return ret;
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}
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ret = nvkm_memory_map(blob, 0, gsb->vmm, vma, NULL, 0);
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if (ret)
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goto end;
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/* Reset and set the falcon up */
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ret = nvkm_falcon_reset(falcon);
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if (ret)
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goto end;
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nvkm_falcon_bind_context(falcon, gsb->inst);
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/* Load the HS bootloader into the falcon's IMEM/DMEM */
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ret = sb->acr->func->load(sb->acr, falcon, blob, vma->addr);
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if (ret < 0)
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goto end;
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start_address = ret;
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/* Disable interrupts as we will poll for the HALT bit */
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nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false);
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/* Set default error value in mailbox register */
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nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
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/* Start the HS bootloader */
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nvkm_falcon_set_start_addr(falcon, start_address);
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nvkm_falcon_start(falcon);
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ret = nvkm_falcon_wait_for_halt(falcon, 100);
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if (ret)
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goto end;
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/*
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* The mailbox register contains the (positive) error code - return this
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* to the caller
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*/
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ret = nvkm_falcon_rd32(falcon, 0x040);
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end:
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/* Reenable interrupts */
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nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true);
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/* We don't need the ACR firmware anymore */
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nvkm_vmm_put(gsb->vmm, &vma);
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nvkm_falcon_put(falcon, subdev);
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return ret;
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}
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int
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gm200_secboot_oneinit(struct nvkm_secboot *sb)
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{
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struct gm200_secboot *gsb = gm200_secboot(sb);
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struct nvkm_device *device = sb->subdev.device;
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int ret;
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/* Allocate instance block and VM */
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, true,
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&gsb->inst);
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if (ret)
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return ret;
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ret = nvkm_vmm_new(device, 0, 600 * 1024, NULL, 0, NULL, "acr",
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&gsb->vmm);
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if (ret)
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return ret;
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atomic_inc(&gsb->vmm->engref[NVKM_SUBDEV_PMU]);
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gsb->vmm->debug = gsb->base.subdev.debug;
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ret = nvkm_vmm_join(gsb->vmm, gsb->inst);
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if (ret)
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return ret;
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if (sb->acr->func->oneinit) {
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ret = sb->acr->func->oneinit(sb->acr, sb);
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if (ret)
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return ret;
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}
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return 0;
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}
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int
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gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend)
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{
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int ret = 0;
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if (sb->acr->func->fini)
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ret = sb->acr->func->fini(sb->acr, sb, suspend);
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return ret;
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}
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void *
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gm200_secboot_dtor(struct nvkm_secboot *sb)
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{
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struct gm200_secboot *gsb = gm200_secboot(sb);
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sb->acr->func->dtor(sb->acr);
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nvkm_vmm_part(gsb->vmm, gsb->inst);
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nvkm_vmm_unref(&gsb->vmm);
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nvkm_memory_unref(&gsb->inst);
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return gsb;
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}
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static const struct nvkm_secboot_func
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gm200_secboot = {
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.dtor = gm200_secboot_dtor,
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.oneinit = gm200_secboot_oneinit,
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.fini = gm200_secboot_fini,
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.run_blob = gm200_secboot_run_blob,
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};
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int
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gm200_secboot_new(struct nvkm_device *device, int index,
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struct nvkm_secboot **psb)
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{
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int ret;
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struct gm200_secboot *gsb;
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struct nvkm_acr *acr;
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acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
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BIT(NVKM_SECBOOT_FALCON_GPCCS));
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if (IS_ERR(acr))
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return PTR_ERR(acr);
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gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
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if (!gsb) {
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psb = NULL;
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return -ENOMEM;
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}
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*psb = &gsb->base;
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ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base);
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if (ret)
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return ret;
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return 0;
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}
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MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin");
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