214 lines
7.3 KiB
C
214 lines
7.3 KiB
C
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Secure boot is the process by which NVIDIA-signed firmware is loaded into
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* some of the falcons of a GPU. For production devices this is the only way
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* for the firmware to access useful (but sensitive) registers.
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*
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* A Falcon microprocessor supporting advanced security modes can run in one of
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* three modes:
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*
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* - Non-secure (NS). In this mode, functionality is similar to Falcon
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* architectures before security modes were introduced (pre-Maxwell), but
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* capability is restricted. In particular, certain registers may be
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* inaccessible for reads and/or writes, and physical memory access may be
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* disabled (on certain Falcon instances). This is the only possible mode that
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* can be used if you don't have microcode cryptographically signed by NVIDIA.
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*
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* - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's
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* not possible to read or write any Falcon internal state or Falcon registers
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* from outside the Falcon (for example, from the host system). The only way
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* to enable this mode is by loading microcode that has been signed by NVIDIA.
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* (The loading process involves tagging the IMEM block as secure, writing the
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* signature into a Falcon register, and starting execution. The hardware will
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* validate the signature, and if valid, grant HS privileges.)
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*
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* - Light Secure (LS). In this mode, the microprocessor has more privileges
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* than NS but fewer than HS. Some of the microprocessor state is visible to
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* host software to ease debugging. The only way to enable this mode is by HS
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* microcode enabling LS mode. Some privileges available to HS mode are not
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* available here. LS mode is introduced in GM20x.
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*
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* Secure boot consists in temporarily switching a HS-capable falcon (typically
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* PMU) into HS mode in order to validate the LS firmwares of managed falcons,
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* load them, and switch managed falcons into LS mode. Once secure boot
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* completes, no falcon remains in HS mode.
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*
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* Secure boot requires a write-protected memory region (WPR) which can only be
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* written by the secure falcon. On dGPU, the driver sets up the WPR region in
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* video memory. On Tegra, it is set up by the bootloader and its location and
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* size written into memory controller registers.
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*
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* The secure boot process takes place as follows:
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*
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* 1) A LS blob is constructed that contains all the LS firmwares we want to
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* load, along with their signatures and bootloaders.
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*
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* 2) A HS blob (also called ACR) is created that contains the signed HS
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* firmware in charge of loading the LS firmwares into their respective
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* falcons.
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*
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* 3) The HS blob is loaded (via its own bootloader) and executed on the
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* HS-capable falcon. It authenticates itself, switches the secure falcon to
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* HS mode and setup the WPR region around the LS blob (dGPU) or copies the
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* LS blob into the WPR region (Tegra).
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*
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* 4) The LS blob is now secure from all external tampering. The HS falcon
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* checks the signatures of the LS firmwares and, if valid, switches the
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* managed falcons to LS mode and makes them ready to run the LS firmware.
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*
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* 5) The managed falcons remain in LS mode and can be started.
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*
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*/
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#include "priv.h"
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#include "acr.h"
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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#include <subdev/pmu.h>
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#include <engine/sec2.h>
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const char *
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nvkm_secboot_falcon_name[] = {
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[NVKM_SECBOOT_FALCON_PMU] = "PMU",
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[NVKM_SECBOOT_FALCON_RESERVED] = "<reserved>",
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[NVKM_SECBOOT_FALCON_FECS] = "FECS",
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[NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS",
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[NVKM_SECBOOT_FALCON_SEC2] = "SEC2",
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[NVKM_SECBOOT_FALCON_END] = "<invalid>",
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};
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/**
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* nvkm_secboot_reset() - reset specified falcon
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*/
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int
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nvkm_secboot_reset(struct nvkm_secboot *sb, unsigned long falcon_mask)
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{
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/* Unmanaged falcon? */
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if ((falcon_mask | sb->acr->managed_falcons) != sb->acr->managed_falcons) {
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nvkm_error(&sb->subdev, "cannot reset unmanaged falcon!\n");
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return -EINVAL;
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}
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return sb->acr->func->reset(sb->acr, sb, falcon_mask);
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}
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/**
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* nvkm_secboot_is_managed() - check whether a given falcon is securely-managed
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*/
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bool
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nvkm_secboot_is_managed(struct nvkm_secboot *sb, enum nvkm_secboot_falcon fid)
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{
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if (!sb)
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return false;
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return sb->acr->managed_falcons & BIT(fid);
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}
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static int
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nvkm_secboot_oneinit(struct nvkm_subdev *subdev)
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{
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struct nvkm_secboot *sb = nvkm_secboot(subdev);
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int ret = 0;
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switch (sb->acr->boot_falcon) {
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case NVKM_SECBOOT_FALCON_PMU:
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sb->halt_falcon = sb->boot_falcon = subdev->device->pmu->falcon;
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break;
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case NVKM_SECBOOT_FALCON_SEC2:
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/* we must keep SEC2 alive forever since ACR will run on it */
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nvkm_engine_ref(&subdev->device->sec2->engine);
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sb->boot_falcon = subdev->device->sec2->falcon;
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sb->halt_falcon = subdev->device->pmu->falcon;
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break;
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default:
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nvkm_error(subdev, "Unmanaged boot falcon %s!\n",
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nvkm_secboot_falcon_name[sb->acr->boot_falcon]);
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return -EINVAL;
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}
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nvkm_debug(subdev, "using %s falcon for ACR\n", sb->boot_falcon->name);
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/* Call chip-specific init function */
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if (sb->func->oneinit)
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ret = sb->func->oneinit(sb);
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if (ret) {
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nvkm_error(subdev, "Secure Boot initialization failed: %d\n",
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ret);
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return ret;
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}
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return 0;
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}
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static int
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nvkm_secboot_fini(struct nvkm_subdev *subdev, bool suspend)
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{
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struct nvkm_secboot *sb = nvkm_secboot(subdev);
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int ret = 0;
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if (sb->func->fini)
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ret = sb->func->fini(sb, suspend);
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return ret;
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}
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static void *
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nvkm_secboot_dtor(struct nvkm_subdev *subdev)
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{
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struct nvkm_secboot *sb = nvkm_secboot(subdev);
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void *ret = NULL;
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if (sb->func->dtor)
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ret = sb->func->dtor(sb);
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return ret;
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}
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static const struct nvkm_subdev_func
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nvkm_secboot = {
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.oneinit = nvkm_secboot_oneinit,
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.fini = nvkm_secboot_fini,
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.dtor = nvkm_secboot_dtor,
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};
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int
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nvkm_secboot_ctor(const struct nvkm_secboot_func *func, struct nvkm_acr *acr,
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struct nvkm_device *device, int index,
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struct nvkm_secboot *sb)
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{
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unsigned long fid;
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nvkm_subdev_ctor(&nvkm_secboot, device, index, &sb->subdev);
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sb->func = func;
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sb->acr = acr;
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acr->subdev = &sb->subdev;
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nvkm_debug(&sb->subdev, "securely managed falcons:\n");
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for_each_set_bit(fid, &sb->acr->managed_falcons,
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NVKM_SECBOOT_FALCON_END)
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nvkm_debug(&sb->subdev, "- %s\n",
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nvkm_secboot_falcon_name[fid]);
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return 0;
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}
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