437 lines
11 KiB
C
437 lines
11 KiB
C
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "msgqueue.h"
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#include <engine/falcon.h>
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#include <subdev/secboot.h>
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/* Queues identifiers */
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enum {
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/* High Priority Command Queue for Host -> PMU communication */
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MSGQUEUE_0137C63D_COMMAND_QUEUE_HPQ = 0,
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/* Low Priority Command Queue for Host -> PMU communication */
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MSGQUEUE_0137C63D_COMMAND_QUEUE_LPQ = 1,
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/* Message queue for PMU -> Host communication */
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MSGQUEUE_0137C63D_MESSAGE_QUEUE = 4,
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MSGQUEUE_0137C63D_NUM_QUEUES = 5,
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};
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struct msgqueue_0137c63d {
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struct nvkm_msgqueue base;
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struct nvkm_msgqueue_queue queue[MSGQUEUE_0137C63D_NUM_QUEUES];
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};
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#define msgqueue_0137c63d(q) \
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container_of(q, struct msgqueue_0137c63d, base)
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struct msgqueue_0137bca5 {
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struct msgqueue_0137c63d base;
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u64 wpr_addr;
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};
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#define msgqueue_0137bca5(q) \
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container_of(container_of(q, struct msgqueue_0137c63d, base), \
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struct msgqueue_0137bca5, base);
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static struct nvkm_msgqueue_queue *
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msgqueue_0137c63d_cmd_queue(struct nvkm_msgqueue *queue,
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enum msgqueue_msg_priority priority)
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{
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struct msgqueue_0137c63d *priv = msgqueue_0137c63d(queue);
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const struct nvkm_subdev *subdev = priv->base.falcon->owner;
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switch (priority) {
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case MSGQUEUE_MSG_PRIORITY_HIGH:
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return &priv->queue[MSGQUEUE_0137C63D_COMMAND_QUEUE_HPQ];
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case MSGQUEUE_MSG_PRIORITY_LOW:
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return &priv->queue[MSGQUEUE_0137C63D_COMMAND_QUEUE_LPQ];
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default:
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nvkm_error(subdev, "invalid command queue!\n");
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return ERR_PTR(-EINVAL);
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}
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}
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static void
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msgqueue_0137c63d_process_msgs(struct nvkm_msgqueue *queue)
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{
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struct msgqueue_0137c63d *priv = msgqueue_0137c63d(queue);
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struct nvkm_msgqueue_queue *q_queue =
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&priv->queue[MSGQUEUE_0137C63D_MESSAGE_QUEUE];
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nvkm_msgqueue_process_msgs(&priv->base, q_queue);
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}
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/* Init unit */
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#define MSGQUEUE_0137C63D_UNIT_INIT 0x07
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enum {
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INIT_MSG_INIT = 0x0,
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};
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static void
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init_gen_cmdline(struct nvkm_msgqueue *queue, void *buf)
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{
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struct {
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u32 reserved;
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u32 freq_hz;
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u32 trace_size;
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u32 trace_dma_base;
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u16 trace_dma_base1;
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u8 trace_dma_offset;
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u32 trace_dma_idx;
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bool secure_mode;
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bool raise_priv_sec;
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struct {
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u32 dma_base;
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u16 dma_base1;
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u8 dma_offset;
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u16 fb_size;
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u8 dma_idx;
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} gc6_ctx;
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u8 pad;
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} *args = buf;
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args->secure_mode = 1;
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}
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/* forward declaration */
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static int acr_init_wpr(struct nvkm_msgqueue *queue);
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static int
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init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr)
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{
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struct msgqueue_0137c63d *priv = msgqueue_0137c63d(_queue);
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struct {
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struct nvkm_msgqueue_msg base;
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u8 pad;
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u16 os_debug_entry_point;
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struct {
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u16 size;
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u16 offset;
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u8 index;
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u8 pad;
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} queue_info[MSGQUEUE_0137C63D_NUM_QUEUES];
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u16 sw_managed_area_offset;
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u16 sw_managed_area_size;
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} *init = (void *)hdr;
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const struct nvkm_subdev *subdev = _queue->falcon->owner;
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int i;
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if (init->base.hdr.unit_id != MSGQUEUE_0137C63D_UNIT_INIT) {
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nvkm_error(subdev, "expected message from init unit\n");
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return -EINVAL;
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}
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if (init->base.msg_type != INIT_MSG_INIT) {
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nvkm_error(subdev, "expected PMU init msg\n");
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return -EINVAL;
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}
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for (i = 0; i < MSGQUEUE_0137C63D_NUM_QUEUES; i++) {
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struct nvkm_msgqueue_queue *queue = &priv->queue[i];
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mutex_init(&queue->mutex);
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queue->index = init->queue_info[i].index;
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queue->offset = init->queue_info[i].offset;
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queue->size = init->queue_info[i].size;
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if (i != MSGQUEUE_0137C63D_MESSAGE_QUEUE) {
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queue->head_reg = 0x4a0 + (queue->index * 4);
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queue->tail_reg = 0x4b0 + (queue->index * 4);
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} else {
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queue->head_reg = 0x4c8;
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queue->tail_reg = 0x4cc;
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}
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nvkm_debug(subdev,
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"queue %d: index %d, offset 0x%08x, size 0x%08x\n",
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i, queue->index, queue->offset, queue->size);
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}
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/* Complete initialization by initializing WPR region */
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return acr_init_wpr(&priv->base);
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}
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static const struct nvkm_msgqueue_init_func
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msgqueue_0137c63d_init_func = {
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.gen_cmdline = init_gen_cmdline,
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.init_callback = init_callback,
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};
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/* ACR unit */
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#define MSGQUEUE_0137C63D_UNIT_ACR 0x0a
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enum {
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ACR_CMD_INIT_WPR_REGION = 0x00,
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ACR_CMD_BOOTSTRAP_FALCON = 0x01,
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ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS = 0x03,
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};
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static void
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acr_init_wpr_callback(struct nvkm_msgqueue *queue,
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struct nvkm_msgqueue_hdr *hdr)
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{
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struct {
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struct nvkm_msgqueue_msg base;
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u32 error_code;
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} *msg = (void *)hdr;
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const struct nvkm_subdev *subdev = queue->falcon->owner;
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if (msg->error_code) {
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nvkm_error(subdev, "ACR WPR init failure: %d\n",
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msg->error_code);
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return;
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}
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nvkm_debug(subdev, "ACR WPR init complete\n");
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complete_all(&queue->init_done);
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}
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static int
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acr_init_wpr(struct nvkm_msgqueue *queue)
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{
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/*
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* region_id: region ID in WPR region
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* wpr_offset: offset in WPR region
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*/
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struct {
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struct nvkm_msgqueue_hdr hdr;
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u8 cmd_type;
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u32 region_id;
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u32 wpr_offset;
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} cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;
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cmd.hdr.size = sizeof(cmd);
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cmd.cmd_type = ACR_CMD_INIT_WPR_REGION;
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cmd.region_id = 0x01;
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cmd.wpr_offset = 0x00;
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nvkm_msgqueue_post(queue, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr,
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acr_init_wpr_callback, NULL, false);
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return 0;
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}
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static void
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acr_boot_falcon_callback(struct nvkm_msgqueue *priv,
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struct nvkm_msgqueue_hdr *hdr)
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{
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struct acr_bootstrap_falcon_msg {
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struct nvkm_msgqueue_msg base;
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u32 falcon_id;
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} *msg = (void *)hdr;
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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u32 falcon_id = msg->falcon_id;
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if (falcon_id >= NVKM_SECBOOT_FALCON_END) {
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nvkm_error(subdev, "in bootstrap falcon callback:\n");
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nvkm_error(subdev, "invalid falcon ID 0x%x\n", falcon_id);
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return;
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}
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nvkm_debug(subdev, "%s booted\n", nvkm_secboot_falcon_name[falcon_id]);
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}
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enum {
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ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES = 0,
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ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO = 1,
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};
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static int
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acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)
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{
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DECLARE_COMPLETION_ONSTACK(completed);
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/*
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* flags - Flag specifying RESET or no RESET.
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* falcon id - Falcon id specifying falcon to bootstrap.
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*/
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struct {
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struct nvkm_msgqueue_hdr hdr;
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u8 cmd_type;
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u32 flags;
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u32 falcon_id;
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} cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;
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cmd.hdr.size = sizeof(cmd);
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cmd.cmd_type = ACR_CMD_BOOTSTRAP_FALCON;
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cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
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cmd.falcon_id = falcon;
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nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr,
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acr_boot_falcon_callback, &completed, true);
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if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000)))
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return -ETIMEDOUT;
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return 0;
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}
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static void
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acr_boot_multiple_falcons_callback(struct nvkm_msgqueue *priv,
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struct nvkm_msgqueue_hdr *hdr)
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{
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struct acr_bootstrap_falcon_msg {
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struct nvkm_msgqueue_msg base;
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u32 falcon_mask;
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} *msg = (void *)hdr;
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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unsigned long falcon_mask = msg->falcon_mask;
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u32 falcon_id, falcon_treated = 0;
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for_each_set_bit(falcon_id, &falcon_mask, NVKM_SECBOOT_FALCON_END) {
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nvkm_debug(subdev, "%s booted\n",
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nvkm_secboot_falcon_name[falcon_id]);
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falcon_treated |= BIT(falcon_id);
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}
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if (falcon_treated != msg->falcon_mask) {
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nvkm_error(subdev, "in bootstrap falcon callback:\n");
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nvkm_error(subdev, "invalid falcon mask 0x%x\n",
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msg->falcon_mask);
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return;
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}
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}
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static int
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acr_boot_multiple_falcons(struct nvkm_msgqueue *priv, unsigned long falcon_mask)
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{
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DECLARE_COMPLETION_ONSTACK(completed);
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/*
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* flags - Flag specifying RESET or no RESET.
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* falcon id - Falcon id specifying falcon to bootstrap.
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*/
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struct {
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struct nvkm_msgqueue_hdr hdr;
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u8 cmd_type;
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u32 flags;
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u32 falcon_mask;
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u32 use_va_mask;
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u32 wpr_lo;
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u32 wpr_hi;
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} cmd;
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struct msgqueue_0137bca5 *queue = msgqueue_0137bca5(priv);
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memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;
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cmd.hdr.size = sizeof(cmd);
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cmd.cmd_type = ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS;
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cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
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cmd.falcon_mask = falcon_mask;
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cmd.wpr_lo = lower_32_bits(queue->wpr_addr);
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cmd.wpr_hi = upper_32_bits(queue->wpr_addr);
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nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr,
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acr_boot_multiple_falcons_callback, &completed, true);
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if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000)))
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return -ETIMEDOUT;
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return 0;
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}
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||
|
|
static const struct nvkm_msgqueue_acr_func
|
||
|
|
msgqueue_0137c63d_acr_func = {
|
||
|
|
.boot_falcon = acr_boot_falcon,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvkm_msgqueue_acr_func
|
||
|
|
msgqueue_0137bca5_acr_func = {
|
||
|
|
.boot_falcon = acr_boot_falcon,
|
||
|
|
.boot_multiple_falcons = acr_boot_multiple_falcons,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void
|
||
|
|
msgqueue_0137c63d_dtor(struct nvkm_msgqueue *queue)
|
||
|
|
{
|
||
|
|
kfree(msgqueue_0137c63d(queue));
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_msgqueue_func
|
||
|
|
msgqueue_0137c63d_func = {
|
||
|
|
.init_func = &msgqueue_0137c63d_init_func,
|
||
|
|
.acr_func = &msgqueue_0137c63d_acr_func,
|
||
|
|
.cmd_queue = msgqueue_0137c63d_cmd_queue,
|
||
|
|
.recv = msgqueue_0137c63d_process_msgs,
|
||
|
|
.dtor = msgqueue_0137c63d_dtor,
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
msgqueue_0137c63d_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb,
|
||
|
|
struct nvkm_msgqueue **queue)
|
||
|
|
{
|
||
|
|
struct msgqueue_0137c63d *ret;
|
||
|
|
|
||
|
|
ret = kzalloc(sizeof(*ret), GFP_KERNEL);
|
||
|
|
if (!ret)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
*queue = &ret->base;
|
||
|
|
|
||
|
|
nvkm_msgqueue_ctor(&msgqueue_0137c63d_func, falcon, &ret->base);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_msgqueue_func
|
||
|
|
msgqueue_0137bca5_func = {
|
||
|
|
.init_func = &msgqueue_0137c63d_init_func,
|
||
|
|
.acr_func = &msgqueue_0137bca5_acr_func,
|
||
|
|
.cmd_queue = msgqueue_0137c63d_cmd_queue,
|
||
|
|
.recv = msgqueue_0137c63d_process_msgs,
|
||
|
|
.dtor = msgqueue_0137c63d_dtor,
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
msgqueue_0137bca5_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb,
|
||
|
|
struct nvkm_msgqueue **queue)
|
||
|
|
{
|
||
|
|
struct msgqueue_0137bca5 *ret;
|
||
|
|
|
||
|
|
ret = kzalloc(sizeof(*ret), GFP_KERNEL);
|
||
|
|
if (!ret)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
*queue = &ret->base.base;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* FIXME this must be set to the address of a *GPU* mapping within the
|
||
|
|
* ACR address space!
|
||
|
|
*/
|
||
|
|
/* ret->wpr_addr = sb->wpr_addr; */
|
||
|
|
|
||
|
|
nvkm_msgqueue_ctor(&msgqueue_0137bca5_func, falcon, &ret->base.base);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|