254 lines
6.9 KiB
C
254 lines
6.9 KiB
C
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_GPU_H__
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#define __MSM_GPU_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "msm_drv.h"
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#include "msm_fence.h"
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#include "msm_ringbuffer.h"
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struct msm_gem_submit;
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struct msm_gpu_perfcntr;
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struct msm_gpu_config {
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const char *ioname;
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const char *irqname;
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uint64_t va_start;
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uint64_t va_end;
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unsigned int nr_rings;
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};
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/* So far, with hardware that I've seen to date, we can have:
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* + zero, one, or two z180 2d cores
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* + a3xx or a2xx 3d core, which share a common CP (the firmware
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* for the CP seems to implement some different PM4 packet types
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* but the basics of cmdstream submission are the same)
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*
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* Which means that the eventual complete "class" hierarchy, once
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* support for all past and present hw is in place, becomes:
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* + msm_gpu
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* + adreno_gpu
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* + a3xx_gpu
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* + a2xx_gpu
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* + z180_gpu
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*/
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struct msm_gpu_funcs {
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int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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int (*hw_init)(struct msm_gpu *gpu);
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int (*pm_suspend)(struct msm_gpu *gpu);
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int (*pm_resume)(struct msm_gpu *gpu);
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void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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irqreturn_t (*irq)(struct msm_gpu *irq);
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struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
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void (*recover)(struct msm_gpu *gpu);
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void (*destroy)(struct msm_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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/* show GPU status in debugfs: */
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void (*show)(struct msm_gpu *gpu, struct seq_file *m);
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#endif
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};
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struct msm_gpu {
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const char *name;
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struct drm_device *dev;
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struct platform_device *pdev;
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const struct msm_gpu_funcs *funcs;
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/* performance counters (hw & sw): */
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spinlock_t perf_lock;
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bool perfcntr_active;
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struct {
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bool active;
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ktime_t time;
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} last_sample;
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uint32_t totaltime, activetime; /* sw counters */
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uint32_t last_cntrs[5]; /* hw counters */
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const struct msm_gpu_perfcntr *perfcntrs;
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uint32_t num_perfcntrs;
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struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
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int nr_rings;
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/* list of GEM active objects: */
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struct list_head active_list;
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/* does gpu need hw_init? */
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bool needs_hw_init;
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/* worker for handling active-list retiring: */
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struct work_struct retire_work;
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void __iomem *mmio;
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int irq;
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struct msm_gem_address_space *aspace;
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/* Power Control: */
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struct regulator *gpu_reg, *gpu_cx;
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struct clk **grp_clks;
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int nr_clocks;
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struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
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uint32_t fast_rate, bus_freq;
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#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
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struct msm_bus_scale_pdata *bus_scale_table;
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uint32_t bsc;
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#endif
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/* Hang and Inactivity Detection:
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*/
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#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
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#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
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#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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struct work_struct recover_work;
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struct drm_gem_object *memptrs_bo;
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};
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/* It turns out that all targets use the same ringbuffer size */
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#define MSM_GPU_RINGBUFFER_SZ SZ_32K
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#define MSM_GPU_RINGBUFFER_BLKSIZE 32
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#define MSM_GPU_RB_CNTL_DEFAULT \
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(AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
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AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
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static inline bool msm_gpu_active(struct msm_gpu *gpu)
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{
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int i;
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for (i = 0; i < gpu->nr_rings; i++) {
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struct msm_ringbuffer *ring = gpu->rb[i];
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if (ring->seqno > ring->memptrs->fence)
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return true;
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}
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return false;
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}
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/* Perf-Counters:
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* The select_reg and select_val are just there for the benefit of the child
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* class that actually enables the perf counter.. but msm_gpu base class
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* will handle sampling/displaying the counters.
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*/
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struct msm_gpu_perfcntr {
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uint32_t select_reg;
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uint32_t sample_reg;
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uint32_t select_val;
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const char *name;
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};
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struct msm_gpu_submitqueue {
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int id;
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u32 flags;
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u32 prio;
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int faults;
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struct list_head node;
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struct kref ref;
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};
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static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
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{
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msm_writel(data, gpu->mmio + (reg << 2));
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}
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static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
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{
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return msm_readl(gpu->mmio + (reg << 2));
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}
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static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
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{
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uint32_t val = gpu_read(gpu, reg);
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val &= ~mask;
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gpu_write(gpu, reg, val | or);
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}
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static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
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{
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u64 val;
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/*
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* Why not a readq here? Two reasons: 1) many of the LO registers are
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* not quad word aligned and 2) the GPU hardware designers have a bit
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* of a history of putting registers where they fit, especially in
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* spins. The longer a GPU family goes the higher the chance that
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* we'll get burned. We could do a series of validity checks if we
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* wanted to, but really is a readq() that much better? Nah.
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*/
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/*
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* For some lo/hi registers (like perfcounters), the hi value is latched
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* when the lo is read, so make sure to read the lo first to trigger
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* that
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*/
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val = (u64) msm_readl(gpu->mmio + (lo << 2));
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val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
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return val;
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}
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static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
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{
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/* Why not a writeq here? Read the screed above */
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msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
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msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu);
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int msm_gpu_pm_resume(struct msm_gpu *gpu);
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int msm_gpu_hw_init(struct msm_gpu *gpu);
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void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
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void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
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int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
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uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
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void msm_gpu_retire(struct msm_gpu *gpu);
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void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
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const char *name, struct msm_gpu_config *config);
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void msm_gpu_cleanup(struct msm_gpu *gpu);
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struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
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void __init adreno_register(void);
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void __exit adreno_unregister(void);
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static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
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{
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if (queue)
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kref_put(&queue->ref, msm_submitqueue_destroy);
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}
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#endif /* __MSM_GPU_H__ */
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