121 lines
3.9 KiB
C
121 lines
3.9 KiB
C
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/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_GUC_H_
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#define _INTEL_GUC_H_
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#include "intel_uncore.h"
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#include "intel_guc_fw.h"
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#include "intel_guc_fwif.h"
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#include "intel_guc_ct.h"
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#include "intel_guc_log.h"
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#include "intel_uc_fw.h"
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#include "i915_guc_reg.h"
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#include "i915_vma.h"
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/*
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* Top level structure of GuC. It handles firmware loading and manages client
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* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
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* ExecList submission.
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*/
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struct intel_guc {
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struct intel_uc_fw fw;
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struct intel_guc_log log;
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struct intel_guc_ct ct;
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/* Log snapshot if GuC errors during load */
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struct drm_i915_gem_object *load_err_log;
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/* intel_guc_recv interrupt related state */
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bool interrupts_enabled;
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struct i915_vma *ads_vma;
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struct i915_vma *stage_desc_pool;
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void *stage_desc_pool_vaddr;
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struct ida stage_ids;
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struct i915_guc_client *execbuf_client;
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DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
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/* Cyclic counter mod pagesize */
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u32 db_cacheline;
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/* GuC's FW specific registers used in MMIO send */
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struct {
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u32 base;
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unsigned int count;
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enum forcewake_domains fw_domains;
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} send_regs;
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/* To serialize the intel_guc_send actions */
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struct mutex send_mutex;
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/* GuC's FW specific send function */
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int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
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/* GuC's FW specific notify function */
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void (*notify)(struct intel_guc *guc);
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};
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static
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inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
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{
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return guc->send(guc, action, len);
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}
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static inline void intel_guc_notify(struct intel_guc *guc)
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{
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guc->notify(guc);
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}
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/*
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* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
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* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
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* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
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* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
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*/
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static inline u32 guc_ggtt_offset(struct i915_vma *vma)
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{
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u32 offset = i915_ggtt_offset(vma);
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GEM_BUG_ON(offset < GUC_WOPCM_TOP);
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GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
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return offset;
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}
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void intel_guc_init_early(struct intel_guc *guc);
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void intel_guc_init_send_regs(struct intel_guc *guc);
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void intel_guc_init_params(struct intel_guc *guc);
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
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int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
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int intel_guc_sample_forcewake(struct intel_guc *guc);
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int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
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int intel_guc_suspend(struct drm_i915_private *dev_priv);
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int intel_guc_resume(struct drm_i915_private *dev_priv);
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struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
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u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
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#endif
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