403 lines
10 KiB
C
403 lines
10 KiB
C
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Anhua Xu
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
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{
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enum intel_engine_id i;
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struct intel_engine_cs *engine;
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for_each_engine(engine, vgpu->gvt->dev_priv, i) {
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if (!list_empty(workload_q_head(vgpu, i)))
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return true;
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}
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return false;
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}
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struct vgpu_sched_data {
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struct list_head lru_list;
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struct intel_vgpu *vgpu;
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ktime_t sched_in_time;
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ktime_t sched_out_time;
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ktime_t sched_time;
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ktime_t left_ts;
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ktime_t allocated_ts;
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struct vgpu_sched_ctl sched_ctl;
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};
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struct gvt_sched_data {
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struct intel_gvt *gvt;
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struct hrtimer timer;
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unsigned long period;
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struct list_head lru_runq_head;
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};
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static void vgpu_update_timeslice(struct intel_vgpu *pre_vgpu)
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{
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ktime_t delta_ts;
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struct vgpu_sched_data *vgpu_data = pre_vgpu->sched_data;
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delta_ts = vgpu_data->sched_out_time - vgpu_data->sched_in_time;
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vgpu_data->sched_time += delta_ts;
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vgpu_data->left_ts -= delta_ts;
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}
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#define GVT_TS_BALANCE_PERIOD_MS 100
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#define GVT_TS_BALANCE_STAGE_NUM 10
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static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
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{
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struct vgpu_sched_data *vgpu_data;
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struct list_head *pos;
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static uint64_t stage_check;
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int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
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/* The timeslice accumulation reset at stage 0, which is
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* allocated again without adding previous debt.
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*/
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if (stage == 0) {
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int total_weight = 0;
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ktime_t fair_timeslice;
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list_for_each(pos, &sched_data->lru_runq_head) {
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vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
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total_weight += vgpu_data->sched_ctl.weight;
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}
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list_for_each(pos, &sched_data->lru_runq_head) {
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vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
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fair_timeslice = ms_to_ktime(GVT_TS_BALANCE_PERIOD_MS) *
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vgpu_data->sched_ctl.weight /
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total_weight;
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vgpu_data->allocated_ts = fair_timeslice;
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vgpu_data->left_ts = vgpu_data->allocated_ts;
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}
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} else {
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list_for_each(pos, &sched_data->lru_runq_head) {
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vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
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/* timeslice for next 100ms should add the left/debt
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* slice of previous stages.
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*/
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vgpu_data->left_ts += vgpu_data->allocated_ts;
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}
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}
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}
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static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
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{
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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enum intel_engine_id i;
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struct intel_engine_cs *engine;
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struct vgpu_sched_data *vgpu_data;
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ktime_t cur_time;
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/* no need to schedule if next_vgpu is the same with current_vgpu,
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* let scheduler chose next_vgpu again by setting it to NULL.
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*/
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if (scheduler->next_vgpu == scheduler->current_vgpu) {
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scheduler->next_vgpu = NULL;
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return;
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}
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/*
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* after the flag is set, workload dispatch thread will
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* stop dispatching workload for current vgpu
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*/
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scheduler->need_reschedule = true;
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/* still have uncompleted workload? */
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for_each_engine(engine, gvt->dev_priv, i) {
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if (scheduler->current_workload[i])
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return;
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}
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cur_time = ktime_get();
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if (scheduler->current_vgpu) {
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vgpu_data = scheduler->current_vgpu->sched_data;
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vgpu_data->sched_out_time = cur_time;
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vgpu_update_timeslice(scheduler->current_vgpu);
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}
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vgpu_data = scheduler->next_vgpu->sched_data;
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vgpu_data->sched_in_time = cur_time;
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/* switch current vgpu */
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scheduler->current_vgpu = scheduler->next_vgpu;
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scheduler->next_vgpu = NULL;
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scheduler->need_reschedule = false;
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/* wake up workload dispatch thread */
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for_each_engine(engine, gvt->dev_priv, i)
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wake_up(&scheduler->waitq[i]);
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}
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static struct intel_vgpu *find_busy_vgpu(struct gvt_sched_data *sched_data)
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{
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struct vgpu_sched_data *vgpu_data;
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struct intel_vgpu *vgpu = NULL;
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struct list_head *head = &sched_data->lru_runq_head;
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struct list_head *pos;
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/* search a vgpu with pending workload */
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list_for_each(pos, head) {
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vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
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if (!vgpu_has_pending_workload(vgpu_data->vgpu))
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continue;
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/* Return the vGPU only if it has time slice left */
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if (vgpu_data->left_ts > 0) {
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vgpu = vgpu_data->vgpu;
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break;
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}
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}
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return vgpu;
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}
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/* in nanosecond */
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#define GVT_DEFAULT_TIME_SLICE 1000000
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static void tbs_sched_func(struct gvt_sched_data *sched_data)
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{
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struct intel_gvt *gvt = sched_data->gvt;
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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struct vgpu_sched_data *vgpu_data;
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struct intel_vgpu *vgpu = NULL;
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/* no active vgpu or has already had a target */
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if (list_empty(&sched_data->lru_runq_head) || scheduler->next_vgpu)
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goto out;
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vgpu = find_busy_vgpu(sched_data);
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if (vgpu) {
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scheduler->next_vgpu = vgpu;
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/* Move the last used vGPU to the tail of lru_list */
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vgpu_data = vgpu->sched_data;
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list_del_init(&vgpu_data->lru_list);
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list_add_tail(&vgpu_data->lru_list,
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&sched_data->lru_runq_head);
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} else {
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scheduler->next_vgpu = gvt->idle_vgpu;
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}
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out:
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if (scheduler->next_vgpu)
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try_to_schedule_next_vgpu(gvt);
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}
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void intel_gvt_schedule(struct intel_gvt *gvt)
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{
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struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;
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static uint64_t timer_check;
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mutex_lock(&gvt->lock);
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if (test_and_clear_bit(INTEL_GVT_REQUEST_SCHED,
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(void *)&gvt->service_request)) {
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if (!(timer_check++ % GVT_TS_BALANCE_PERIOD_MS))
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gvt_balance_timeslice(sched_data);
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}
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clear_bit(INTEL_GVT_REQUEST_EVENT_SCHED, (void *)&gvt->service_request);
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tbs_sched_func(sched_data);
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mutex_unlock(&gvt->lock);
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}
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static enum hrtimer_restart tbs_timer_fn(struct hrtimer *timer_data)
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{
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struct gvt_sched_data *data;
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data = container_of(timer_data, struct gvt_sched_data, timer);
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intel_gvt_request_service(data->gvt, INTEL_GVT_REQUEST_SCHED);
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hrtimer_add_expires_ns(&data->timer, data->period);
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return HRTIMER_RESTART;
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}
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static int tbs_sched_init(struct intel_gvt *gvt)
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{
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struct intel_gvt_workload_scheduler *scheduler =
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&gvt->scheduler;
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struct gvt_sched_data *data;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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INIT_LIST_HEAD(&data->lru_runq_head);
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hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
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data->timer.function = tbs_timer_fn;
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data->period = GVT_DEFAULT_TIME_SLICE;
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data->gvt = gvt;
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scheduler->sched_data = data;
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return 0;
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}
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static void tbs_sched_clean(struct intel_gvt *gvt)
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{
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struct intel_gvt_workload_scheduler *scheduler =
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&gvt->scheduler;
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struct gvt_sched_data *data = scheduler->sched_data;
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hrtimer_cancel(&data->timer);
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kfree(data);
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scheduler->sched_data = NULL;
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}
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static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu)
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{
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struct vgpu_sched_data *data;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->sched_ctl.weight = vgpu->sched_ctl.weight;
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data->vgpu = vgpu;
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INIT_LIST_HEAD(&data->lru_list);
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vgpu->sched_data = data;
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return 0;
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}
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static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)
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{
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kfree(vgpu->sched_data);
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vgpu->sched_data = NULL;
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}
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static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
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{
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struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data;
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struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
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if (!list_empty(&vgpu_data->lru_list))
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return;
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list_add_tail(&vgpu_data->lru_list, &sched_data->lru_runq_head);
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if (!hrtimer_active(&sched_data->timer))
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hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(),
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sched_data->period), HRTIMER_MODE_ABS);
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}
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static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
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{
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struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
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list_del_init(&vgpu_data->lru_list);
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}
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static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
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.init = tbs_sched_init,
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.clean = tbs_sched_clean,
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.init_vgpu = tbs_sched_init_vgpu,
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.clean_vgpu = tbs_sched_clean_vgpu,
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.start_schedule = tbs_sched_start_schedule,
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.stop_schedule = tbs_sched_stop_schedule,
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};
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int intel_gvt_init_sched_policy(struct intel_gvt *gvt)
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{
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gvt->scheduler.sched_ops = &tbs_schedule_ops;
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return gvt->scheduler.sched_ops->init(gvt);
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}
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void intel_gvt_clean_sched_policy(struct intel_gvt *gvt)
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{
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gvt->scheduler.sched_ops->clean(gvt);
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}
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int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu)
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{
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return vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu);
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}
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void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu)
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{
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vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu);
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}
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void intel_vgpu_start_schedule(struct intel_vgpu *vgpu)
|
||
|
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{
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||
|
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gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);
|
||
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|
||
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vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu);
|
||
|
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}
|
||
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|
||
|
|
void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu)
|
||
|
|
{
|
||
|
|
struct intel_gvt_workload_scheduler *scheduler =
|
||
|
|
&vgpu->gvt->scheduler;
|
||
|
|
int ring_id;
|
||
|
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|
||
|
|
gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);
|
||
|
|
|
||
|
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scheduler->sched_ops->stop_schedule(vgpu);
|
||
|
|
|
||
|
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if (scheduler->next_vgpu == vgpu)
|
||
|
|
scheduler->next_vgpu = NULL;
|
||
|
|
|
||
|
|
if (scheduler->current_vgpu == vgpu) {
|
||
|
|
/* stop workload dispatching */
|
||
|
|
scheduler->need_reschedule = true;
|
||
|
|
scheduler->current_vgpu = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
spin_lock_bh(&scheduler->mmio_context_lock);
|
||
|
|
for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
|
||
|
|
if (scheduler->engine_owner[ring_id] == vgpu) {
|
||
|
|
intel_gvt_switch_mmio(vgpu, NULL, ring_id);
|
||
|
|
scheduler->engine_owner[ring_id] = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
spin_unlock_bh(&scheduler->mmio_context_lock);
|
||
|
|
}
|