367 lines
8.2 KiB
C
367 lines
8.2 KiB
C
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/**************************************************************************
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Copyright © 2006 Dave Airlie
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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#include "dvo.h"
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#define CH7xxx_REG_VID 0x4a
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#define CH7xxx_REG_DID 0x4b
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#define CH7011_VID 0x83 /* 7010 as well */
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#define CH7010B_VID 0x05
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#define CH7009A_VID 0x84
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#define CH7009B_VID 0x85
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#define CH7301_VID 0x95
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#define CH7xxx_VID 0x84
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#define CH7xxx_DID 0x17
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#define CH7010_DID 0x16
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#define CH7xxx_NUM_REGS 0x4c
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#define CH7xxx_CM 0x1c
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#define CH7xxx_CM_XCM (1<<0)
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#define CH7xxx_CM_MCP (1<<2)
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#define CH7xxx_INPUT_CLOCK 0x1d
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#define CH7xxx_GPIO 0x1e
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#define CH7xxx_GPIO_HPIR (1<<3)
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#define CH7xxx_IDF 0x1f
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#define CH7xxx_IDF_HSP (1<<3)
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#define CH7xxx_IDF_VSP (1<<4)
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#define CH7xxx_CONNECTION_DETECT 0x20
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#define CH7xxx_CDET_DVI (1<<5)
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#define CH7301_DAC_CNTL 0x21
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#define CH7301_HOTPLUG 0x23
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#define CH7xxx_TCTL 0x31
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#define CH7xxx_TVCO 0x32
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#define CH7xxx_TPCP 0x33
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#define CH7xxx_TPD 0x34
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#define CH7xxx_TPVT 0x35
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#define CH7xxx_TLPF 0x36
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#define CH7xxx_TCT 0x37
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#define CH7301_TEST_PATTERN 0x48
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#define CH7xxx_PM 0x49
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#define CH7xxx_PM_FPD (1<<0)
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#define CH7301_PM_DACPD0 (1<<1)
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#define CH7301_PM_DACPD1 (1<<2)
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#define CH7301_PM_DACPD2 (1<<3)
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#define CH7xxx_PM_DVIL (1<<6)
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#define CH7xxx_PM_DVIP (1<<7)
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#define CH7301_SYNC_POLARITY 0x56
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#define CH7301_SYNC_RGB_YUV (1<<0)
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#define CH7301_SYNC_POL_DVI (1<<5)
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/** @file
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* driver for the Chrontel 7xxx DVI chip over DVO.
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*/
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static struct ch7xxx_id_struct {
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uint8_t vid;
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char *name;
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} ch7xxx_ids[] = {
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{ CH7011_VID, "CH7011" },
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{ CH7010B_VID, "CH7010B" },
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{ CH7009A_VID, "CH7009A" },
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{ CH7009B_VID, "CH7009B" },
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{ CH7301_VID, "CH7301" },
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};
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static struct ch7xxx_did_struct {
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uint8_t did;
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char *name;
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} ch7xxx_dids[] = {
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{ CH7xxx_DID, "CH7XXX" },
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{ CH7010_DID, "CH7010B" },
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};
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struct ch7xxx_priv {
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bool quiet;
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};
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static char *ch7xxx_get_id(uint8_t vid)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
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if (ch7xxx_ids[i].vid == vid)
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return ch7xxx_ids[i].name;
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}
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return NULL;
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}
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static char *ch7xxx_get_did(uint8_t did)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) {
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if (ch7xxx_dids[i].did == did)
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return ch7xxx_dids[i].name;
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}
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return NULL;
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}
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/** Reads an 8 bit register */
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static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
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{
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struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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u8 out_buf[2];
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u8 in_buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 1,
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.buf = out_buf,
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},
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = in_buf,
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}
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};
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out_buf[0] = addr;
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out_buf[1] = 0;
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if (i2c_transfer(adapter, msgs, 2) == 2) {
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*ch = in_buf[0];
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return true;
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}
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if (!ch7xxx->quiet) {
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DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
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addr, adapter->name, dvo->slave_addr);
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}
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return false;
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}
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/** Writes an 8 bit register */
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static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
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{
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struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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uint8_t out_buf[2];
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struct i2c_msg msg = {
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 2,
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.buf = out_buf,
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};
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out_buf[0] = addr;
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out_buf[1] = ch;
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if (i2c_transfer(adapter, &msg, 1) == 1)
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return true;
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if (!ch7xxx->quiet) {
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DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
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addr, adapter->name, dvo->slave_addr);
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}
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return false;
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}
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static bool ch7xxx_init(struct intel_dvo_device *dvo,
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struct i2c_adapter *adapter)
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{
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/* this will detect the CH7xxx chip on the specified i2c bus */
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struct ch7xxx_priv *ch7xxx;
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uint8_t vendor, device;
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char *name, *devid;
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ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
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if (ch7xxx == NULL)
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return false;
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dvo->i2c_bus = adapter;
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dvo->dev_priv = ch7xxx;
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ch7xxx->quiet = true;
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if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
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goto out;
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name = ch7xxx_get_id(vendor);
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if (!name) {
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DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s slave %d.\n",
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vendor, adapter->name, dvo->slave_addr);
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goto out;
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}
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if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
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goto out;
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devid = ch7xxx_get_did(device);
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if (!devid) {
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DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s slave %d.\n",
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device, adapter->name, dvo->slave_addr);
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goto out;
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}
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ch7xxx->quiet = false;
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DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
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name, vendor, device);
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return true;
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out:
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kfree(ch7xxx);
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return false;
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}
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static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
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{
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uint8_t cdet, orig_pm, pm;
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ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);
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pm = orig_pm;
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pm &= ~CH7xxx_PM_FPD;
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pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;
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ch7xxx_writeb(dvo, CH7xxx_PM, pm);
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ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);
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ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);
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if (cdet & CH7xxx_CDET_DVI)
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return connector_status_connected;
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return connector_status_disconnected;
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}
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static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode)
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{
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if (mode->clock > 165000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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uint8_t tvco, tpcp, tpd, tlpf, idf;
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if (mode->clock <= 65000) {
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tvco = 0x23;
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tpcp = 0x08;
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tpd = 0x16;
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tlpf = 0x60;
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} else {
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tvco = 0x2d;
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tpcp = 0x06;
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tpd = 0x26;
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tlpf = 0xa0;
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}
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ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
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ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
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ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
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ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
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ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
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ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
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ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);
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ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
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idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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idf |= CH7xxx_IDF_HSP;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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idf |= CH7xxx_IDF_VSP;
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ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
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}
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/* set the CH7xxx power state */
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static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
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{
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if (enable)
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ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
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else
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ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
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}
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static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
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{
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u8 val;
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ch7xxx_readb(dvo, CH7xxx_PM, &val);
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if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
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return true;
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else
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return false;
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}
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static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
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{
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int i;
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for (i = 0; i < CH7xxx_NUM_REGS; i++) {
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uint8_t val;
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if ((i % 8) == 0)
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DRM_DEBUG_KMS("\n %02X: ", i);
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ch7xxx_readb(dvo, i, &val);
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DRM_DEBUG_KMS("%02X ", val);
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}
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}
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static void ch7xxx_destroy(struct intel_dvo_device *dvo)
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{
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struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
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if (ch7xxx) {
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kfree(ch7xxx);
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dvo->dev_priv = NULL;
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}
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}
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const struct intel_dvo_dev_ops ch7xxx_ops = {
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.init = ch7xxx_init,
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.detect = ch7xxx_detect,
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.mode_valid = ch7xxx_mode_valid,
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.mode_set = ch7xxx_mode_set,
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.dpms = ch7xxx_dpms,
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.get_hw_state = ch7xxx_get_hw_state,
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.dump_regs = ch7xxx_dump_regs,
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.destroy = ch7xxx_destroy,
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};
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