256 lines
6.7 KiB
C
256 lines
6.7 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <drm/amdgpu_drm.h>
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#include "smumgr.h"
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#include "cgs_common.h"
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MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
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MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
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MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
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MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
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MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
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int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
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return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
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return 0;
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}
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int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
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return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
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return 0;
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}
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int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
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return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
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return 0;
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}
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int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
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{
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if (NULL != hwmgr->smumgr_funcs->update_smc_table)
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return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
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return 0;
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}
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uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
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{
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if (NULL != hwmgr->smumgr_funcs->get_offsetof)
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return hwmgr->smumgr_funcs->get_offsetof(type, member);
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return 0;
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}
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int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
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return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
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return 0;
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}
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int smum_get_argument(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->get_argument)
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return hwmgr->smumgr_funcs->get_argument(hwmgr);
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return 0;
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}
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uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
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{
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if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
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return hwmgr->smumgr_funcs->get_mac_definition(value);
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return 0;
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}
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int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
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{
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if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
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return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
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table);
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return 0;
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}
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int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
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return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
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return 0;
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}
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int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL)
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return -EINVAL;
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return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
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}
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int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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if (hwmgr == NULL ||
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hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
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return -EINVAL;
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return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
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hwmgr, msg, parameter);
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}
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int smu_allocate_memory(void *device, uint32_t size,
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enum cgs_gpu_mem_type type,
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uint32_t byte_align, uint64_t *mc_addr,
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void **kptr, void *handle)
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{
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int ret = 0;
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cgs_handle_t cgs_handle;
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if (device == NULL || handle == NULL ||
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mc_addr == NULL || kptr == NULL)
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return -EINVAL;
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ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
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(cgs_handle_t *)handle);
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if (ret)
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return -ENOMEM;
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cgs_handle = *(cgs_handle_t *)handle;
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ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
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if (ret)
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goto error_gmap;
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ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
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if (ret)
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goto error_kmap;
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return 0;
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error_kmap:
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cgs_gunmap_gpu_mem(device, cgs_handle);
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error_gmap:
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cgs_free_gpu_mem(device, cgs_handle);
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return ret;
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}
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int smu_free_memory(void *device, void *handle)
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{
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cgs_handle_t cgs_handle = (cgs_handle_t)handle;
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if (device == NULL || handle == NULL)
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return -EINVAL;
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cgs_kunmap_gpu_mem(device, cgs_handle);
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cgs_gunmap_gpu_mem(device, cgs_handle);
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cgs_free_gpu_mem(device, cgs_handle);
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return 0;
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}
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int smum_init_smc_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->init_smc_table)
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return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
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return 0;
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}
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int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
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return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
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return 0;
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}
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int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
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return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
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return 0;
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}
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/*this interface is needed by island ci/vi */
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int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
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return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
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return 0;
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}
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bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
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return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
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return true;
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}
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int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
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struct amd_pp_profile *request)
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{
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if (hwmgr->smumgr_funcs->populate_requested_graphic_levels)
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return hwmgr->smumgr_funcs->populate_requested_graphic_levels(
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hwmgr, request);
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return 0;
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}
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bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
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{
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if (hwmgr->smumgr_funcs->is_hw_avfs_present)
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return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
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return false;
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}
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