149 lines
6.6 KiB
C
149 lines
6.6 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU9_H
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#define SMU9_H
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#pragma pack(push, 1)
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#define ENABLE_DEBUG_FEATURES
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/* Feature Control Defines */
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#define FEATURE_DPM_PREFETCHER_BIT 0
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#define FEATURE_DPM_GFXCLK_BIT 1
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#define FEATURE_DPM_UCLK_BIT 2
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#define FEATURE_DPM_SOCCLK_BIT 3
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#define FEATURE_DPM_UVD_BIT 4
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#define FEATURE_DPM_VCE_BIT 5
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#define FEATURE_ULV_BIT 6
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#define FEATURE_DPM_MP0CLK_BIT 7
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#define FEATURE_DPM_LINK_BIT 8
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#define FEATURE_DPM_DCEFCLK_BIT 9
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#define FEATURE_AVFS_BIT 10
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#define FEATURE_DS_GFXCLK_BIT 11
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#define FEATURE_DS_SOCCLK_BIT 12
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#define FEATURE_DS_LCLK_BIT 13
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#define FEATURE_PPT_BIT 14
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#define FEATURE_TDC_BIT 15
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#define FEATURE_THERMAL_BIT 16
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#define FEATURE_GFX_PER_CU_CG_BIT 17
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#define FEATURE_RM_BIT 18
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#define FEATURE_DS_DCEFCLK_BIT 19
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#define FEATURE_ACDC_BIT 20
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#define FEATURE_VR0HOT_BIT 21
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#define FEATURE_VR1HOT_BIT 22
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#define FEATURE_FW_CTF_BIT 23
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#define FEATURE_LED_DISPLAY_BIT 24
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#define FEATURE_FAN_CONTROL_BIT 25
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#define FEATURE_FAST_PPT_BIT 26
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#define FEATURE_GFX_EDC_BIT 27
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#define FEATURE_ACG_BIT 28
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#define FEATURE_SPARE_29_BIT 29
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#define FEATURE_SPARE_30_BIT 30
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#define FEATURE_SPARE_31_BIT 31
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#define NUM_FEATURES 32
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#define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
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#define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
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#define FFEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
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#define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
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#define FFEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
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#define FFEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
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#define FFEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
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#define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
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#define FFEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
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#define FFEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
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#define FFEATURE_AVFS_MASK (1 << FEATURE_AVFS_BIT )
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#define FFEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
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#define FFEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
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#define FFEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
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#define FFEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
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#define FFEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
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#define FFEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
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#define FFEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
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#define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT )
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#define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
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#define FFEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
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#define FFEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
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#define FFEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
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#define FFEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
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#define FFEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
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#define FFEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
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#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT )
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#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
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#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
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#define FFEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
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#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
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#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
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/* Workload types */
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#define WORKLOAD_VR_BIT 0
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#define WORKLOAD_FRTC_BIT 1
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#define WORKLOAD_VIDEO_BIT 2
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#define WORKLOAD_COMPUTE_BIT 3
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#define NUM_WORKLOADS 4
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/* ULV Client Masks */
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#define ULV_CLIENT_RLC_MASK 0x00000001
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#define ULV_CLIENT_UVD_MASK 0x00000002
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#define ULV_CLIENT_VCE_MASK 0x00000004
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#define ULV_CLIENT_SDMA0_MASK 0x00000008
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#define ULV_CLIENT_SDMA1_MASK 0x00000010
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#define ULV_CLIENT_JPEG_MASK 0x00000020
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#define ULV_CLIENT_GFXCLK_DPM_MASK 0x00000040
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#define ULV_CLIENT_UVD_DPM_MASK 0x00000080
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#define ULV_CLIENT_VCE_DPM_MASK 0x00000100
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#define ULV_CLIENT_MP0CLK_DPM_MASK 0x00000200
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#define ULV_CLIENT_UCLK_DPM_MASK 0x00000400
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#define ULV_CLIENT_SOCCLK_DPM_MASK 0x00000800
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#define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000
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typedef struct {
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/* MP1_EXT_SCRATCH0 */
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uint32_t CurrLevel_GFXCLK : 4;
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uint32_t CurrLevel_UVD : 4;
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uint32_t CurrLevel_VCE : 4;
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uint32_t CurrLevel_LCLK : 4;
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uint32_t CurrLevel_MP0CLK : 4;
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uint32_t CurrLevel_UCLK : 4;
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uint32_t CurrLevel_SOCCLK : 4;
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uint32_t CurrLevel_DCEFCLK : 4;
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/* MP1_EXT_SCRATCH1 */
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uint32_t TargLevel_GFXCLK : 4;
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uint32_t TargLevel_UVD : 4;
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uint32_t TargLevel_VCE : 4;
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uint32_t TargLevel_LCLK : 4;
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uint32_t TargLevel_MP0CLK : 4;
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uint32_t TargLevel_UCLK : 4;
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uint32_t TargLevel_SOCCLK : 4;
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uint32_t TargLevel_DCEFCLK : 4;
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/* MP1_EXT_SCRATCH2-7 */
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uint32_t Reserved[6];
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} FwStatus_t;
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#pragma pack(pop)
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#endif
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