328 lines
11 KiB
C
328 lines
11 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMD_SHARED_H__
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#define __AMD_SHARED_H__
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#include <drm/amd_asic_type.h>
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struct seq_file;
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#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
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/*
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* Chip flags
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*/
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enum amd_chip_flags {
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AMD_ASIC_MASK = 0x0000ffffUL,
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AMD_FLAGS_MASK = 0xffff0000UL,
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AMD_IS_MOBILITY = 0x00010000UL,
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AMD_IS_APU = 0x00020000UL,
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AMD_IS_PX = 0x00040000UL,
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AMD_EXP_HW_SUPPORT = 0x00080000UL,
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};
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enum amd_ip_block_type {
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AMD_IP_BLOCK_TYPE_COMMON,
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AMD_IP_BLOCK_TYPE_GMC,
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AMD_IP_BLOCK_TYPE_IH,
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AMD_IP_BLOCK_TYPE_SMC,
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AMD_IP_BLOCK_TYPE_PSP,
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AMD_IP_BLOCK_TYPE_DCE,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_IP_BLOCK_TYPE_SDMA,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_ACP,
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AMD_IP_BLOCK_TYPE_VCN
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};
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enum amd_clockgating_state {
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AMD_CG_STATE_GATE = 0,
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AMD_CG_STATE_UNGATE,
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};
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enum amd_dpm_forced_level {
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AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
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AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
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AMD_DPM_FORCED_LEVEL_LOW = 0x4,
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AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
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AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
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AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
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};
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enum amd_powergating_state {
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AMD_PG_STATE_GATE = 0,
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AMD_PG_STATE_UNGATE,
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};
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struct amd_vce_state {
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/* vce clocks */
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u32 evclk;
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u32 ecclk;
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/* gpu clocks */
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u32 sclk;
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u32 mclk;
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u8 clk_idx;
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u8 pstate;
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};
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#define AMD_MAX_VCE_LEVELS 6
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enum amd_vce_level {
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AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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};
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enum amd_pp_profile_type {
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AMD_PP_GFX_PROFILE,
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AMD_PP_COMPUTE_PROFILE,
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};
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struct amd_pp_profile {
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enum amd_pp_profile_type type;
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uint32_t min_sclk;
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uint32_t min_mclk;
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uint16_t activity_threshold;
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uint8_t up_hyst;
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uint8_t down_hyst;
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};
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enum amd_fan_ctrl_mode {
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AMD_FAN_CTRL_NONE = 0,
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AMD_FAN_CTRL_MANUAL = 1,
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AMD_FAN_CTRL_AUTO = 2,
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};
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enum pp_clock_type {
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PP_SCLK,
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PP_MCLK,
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PP_PCIE,
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};
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/* CG flags */
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#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
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#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
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#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
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#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
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#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
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#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
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#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
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#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
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#define AMD_CG_SUPPORT_MC_LS (1 << 8)
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#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
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#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
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#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
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#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
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#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
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#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
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#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
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#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
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#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
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#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
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#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
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#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
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#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
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#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
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#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
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/* PG flags */
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#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
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#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
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#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
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#define AMD_PG_SUPPORT_UVD (1 << 3)
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#define AMD_PG_SUPPORT_VCE (1 << 4)
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#define AMD_PG_SUPPORT_CP (1 << 5)
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#define AMD_PG_SUPPORT_GDS (1 << 6)
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#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
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#define AMD_PG_SUPPORT_SDMA (1 << 8)
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#define AMD_PG_SUPPORT_ACP (1 << 9)
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#define AMD_PG_SUPPORT_SAMU (1 << 10)
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#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
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#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
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#define AMD_PG_SUPPORT_MMHUB (1 << 13)
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enum amd_pm_state_type {
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/* not used for dpm */
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POWER_STATE_TYPE_DEFAULT,
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POWER_STATE_TYPE_POWERSAVE,
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/* user selectable states */
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POWER_STATE_TYPE_BATTERY,
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POWER_STATE_TYPE_BALANCED,
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POWER_STATE_TYPE_PERFORMANCE,
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/* internal states */
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POWER_STATE_TYPE_INTERNAL_UVD,
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POWER_STATE_TYPE_INTERNAL_UVD_SD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD2,
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POWER_STATE_TYPE_INTERNAL_UVD_MVC,
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POWER_STATE_TYPE_INTERNAL_BOOT,
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POWER_STATE_TYPE_INTERNAL_THERMAL,
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POWER_STATE_TYPE_INTERNAL_ACPI,
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POWER_STATE_TYPE_INTERNAL_ULV,
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POWER_STATE_TYPE_INTERNAL_3DPERF,
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};
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struct amd_ip_funcs {
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/* Name of IP block */
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char *name;
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/* sets up early driver state (pre sw_init), does not configure hw - Optional */
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int (*early_init)(void *handle);
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/* sets up late driver/hw state (post hw_init) - Optional */
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int (*late_init)(void *handle);
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/* sets up driver state, does not configure hw */
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int (*sw_init)(void *handle);
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/* tears down driver state, does not configure hw */
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int (*sw_fini)(void *handle);
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/* sets up the hw state */
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int (*hw_init)(void *handle);
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/* tears down the hw state */
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int (*hw_fini)(void *handle);
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void (*late_fini)(void *handle);
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/* handles IP specific hw/sw changes for suspend */
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int (*suspend)(void *handle);
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/* handles IP specific hw/sw changes for resume */
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int (*resume)(void *handle);
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/* returns current IP block idle status */
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bool (*is_idle)(void *handle);
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/* poll for idle */
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int (*wait_for_idle)(void *handle);
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/* check soft reset the IP block */
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bool (*check_soft_reset)(void *handle);
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/* pre soft reset the IP block */
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int (*pre_soft_reset)(void *handle);
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/* soft reset the IP block */
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int (*soft_reset)(void *handle);
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/* post soft reset the IP block */
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int (*post_soft_reset)(void *handle);
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/* enable/disable cg for the IP block */
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int (*set_clockgating_state)(void *handle,
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enum amd_clockgating_state state);
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/* enable/disable pg for the IP block */
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int (*set_powergating_state)(void *handle,
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enum amd_powergating_state state);
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/* get current clockgating status */
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void (*get_clockgating_state)(void *handle, u32 *flags);
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};
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enum amd_pp_task;
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enum amd_pp_clock_type;
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struct pp_states_info;
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struct amd_pp_simple_clock_info;
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struct amd_pp_display_configuration;
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struct amd_pp_clock_info;
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struct pp_display_clock_request;
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struct pp_wm_sets_with_clock_ranges_soc15;
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struct pp_clock_levels_with_voltage;
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struct pp_clock_levels_with_latency;
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struct amd_pp_clocks;
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struct amd_pm_funcs {
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/* export for dpm on ci and si */
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int (*pre_set_power_state)(void *handle);
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int (*set_power_state)(void *handle);
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void (*post_set_power_state)(void *handle);
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void (*display_configuration_changed)(void *handle);
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void (*print_power_state)(void *handle, void *ps);
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bool (*vblank_too_short)(void *handle);
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void (*enable_bapm)(void *handle, bool enable);
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int (*check_state_equal)(void *handle,
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void *cps,
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void *rps,
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bool *equal);
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/* export for sysfs */
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int (*get_temperature)(void *handle);
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void (*set_fan_control_mode)(void *handle, u32 mode);
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u32 (*get_fan_control_mode)(void *handle);
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int (*set_fan_speed_percent)(void *handle, u32 speed);
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int (*get_fan_speed_percent)(void *handle, u32 *speed);
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int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
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int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
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int (*get_sclk_od)(void *handle);
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int (*set_sclk_od)(void *handle, uint32_t value);
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int (*get_mclk_od)(void *handle);
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int (*set_mclk_od)(void *handle, uint32_t value);
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int (*read_sensor)(void *handle, int idx, void *value, int *size);
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enum amd_dpm_forced_level (*get_performance_level)(void *handle);
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enum amd_pm_state_type (*get_current_power_state)(void *handle);
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int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
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int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
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int (*get_pp_table)(void *handle, char **table);
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int (*set_pp_table)(void *handle, const char *buf, size_t size);
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void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
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int (*reset_power_profile_state)(void *handle,
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struct amd_pp_profile *request);
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int (*get_power_profile_state)(void *handle,
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struct amd_pp_profile *query);
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int (*set_power_profile_state)(void *handle,
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struct amd_pp_profile *request);
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int (*switch_power_profile)(void *handle,
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enum amd_pp_profile_type type);
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/* export to amdgpu */
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void (*powergate_uvd)(void *handle, bool gate);
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void (*powergate_vce)(void *handle, bool gate);
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struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx);
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int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
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void *input, void *output);
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int (*load_firmware)(void *handle);
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int (*wait_for_fw_loading_complete)(void *handle);
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int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
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/* export to DC */
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u32 (*get_sclk)(void *handle, bool low);
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u32 (*get_mclk)(void *handle, bool low);
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int (*display_configuration_change)(void *handle,
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const struct amd_pp_display_configuration *input);
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int (*get_display_power_level)(void *handle,
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struct amd_pp_simple_clock_info *output);
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int (*get_current_clocks)(void *handle,
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struct amd_pp_clock_info *clocks);
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int (*get_clock_by_type)(void *handle,
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enum amd_pp_clock_type type,
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struct amd_pp_clocks *clocks);
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int (*get_clock_by_type_with_latency)(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int (*get_clock_by_type_with_voltage)(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int (*set_watermarks_for_clocks_ranges)(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int (*display_clock_voltage_request)(void *handle,
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struct pp_display_clock_request *clock);
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int (*get_display_mode_validation_clocks)(void *handle,
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struct amd_pp_simple_clock_info *clocks);
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};
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#endif /* __AMD_SHARED_H__ */
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