1104 lines
30 KiB
C
1104 lines
30 KiB
C
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/*
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* Copyright 2012-14 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_INTERFACE_H_
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#define DC_INTERFACE_H_
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#include "dc_types.h"
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#include "grph_object_defs.h"
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#include "logger_types.h"
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#include "gpio_types.h"
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#include "link_service_types.h"
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#include "grph_object_ctrl_defs.h"
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#include <inc/hw/opp.h>
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#include "inc/hw_sequencer.h"
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#include "inc/compressor.h"
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#include "dml/display_mode_lib.h"
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#define DC_VER "3.1.07"
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#define MAX_SURFACES 3
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#define MAX_STREAMS 6
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#define MAX_SINKS_PER_LINK 4
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/*******************************************************************************
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* Display Core Interfaces
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******************************************************************************/
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struct dc_caps {
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uint32_t max_streams;
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uint32_t max_links;
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uint32_t max_audios;
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uint32_t max_slave_planes;
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uint32_t max_planes;
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uint32_t max_downscale_ratio;
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uint32_t i2c_speed_in_khz;
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unsigned int max_cursor_size;
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unsigned int max_video_width;
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bool dcc_const_color;
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bool dynamic_audio;
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};
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struct dc_dcc_surface_param {
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struct dc_size surface_size;
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enum surface_pixel_format format;
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enum swizzle_mode_values swizzle_mode;
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enum dc_scan_direction scan;
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};
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struct dc_dcc_setting {
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unsigned int max_compressed_blk_size;
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unsigned int max_uncompressed_blk_size;
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bool independent_64b_blks;
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};
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struct dc_surface_dcc_cap {
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union {
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struct {
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struct dc_dcc_setting rgb;
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} grph;
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struct {
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struct dc_dcc_setting luma;
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struct dc_dcc_setting chroma;
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} video;
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};
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bool capable;
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bool const_color_support;
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};
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struct dc_static_screen_events {
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bool cursor_update;
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bool surface_update;
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bool overlay_update;
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};
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/* Forward declaration*/
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struct dc;
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struct dc_plane_state;
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struct dc_state;
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struct dc_cap_funcs {
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bool (*get_dcc_compression_cap)(const struct dc *dc,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output);
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};
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struct dc_stream_state_funcs {
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bool (*adjust_vmin_vmax)(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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int vmin,
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int vmax);
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bool (*get_crtc_position)(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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unsigned int *v_pos,
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unsigned int *nom_v_pos);
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bool (*set_gamut_remap)(struct dc *dc,
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const struct dc_stream_state *stream);
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bool (*program_csc_matrix)(struct dc *dc,
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struct dc_stream_state *stream);
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void (*set_static_screen_events)(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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const struct dc_static_screen_events *events);
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void (*set_dither_option)(struct dc_stream_state *stream,
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enum dc_dither_option option);
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void (*set_dpms)(struct dc *dc,
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struct dc_stream_state *stream,
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bool dpms_off);
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};
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struct link_training_settings;
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struct dc_link_funcs {
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void (*set_drive_settings)(struct dc *dc,
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struct link_training_settings *lt_settings,
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const struct dc_link *link);
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void (*perform_link_training)(struct dc *dc,
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struct dc_link_settings *link_setting,
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bool skip_video_pattern);
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void (*set_preferred_link_settings)(struct dc *dc,
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struct dc_link_settings *link_setting,
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struct dc_link *link);
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void (*enable_hpd)(const struct dc_link *link);
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void (*disable_hpd)(const struct dc_link *link);
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void (*set_test_pattern)(
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struct dc_link *link,
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enum dp_test_pattern test_pattern,
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const struct link_training_settings *p_link_settings,
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const unsigned char *p_custom_pattern,
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unsigned int cust_pattern_size);
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};
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/* Structure to hold configuration flags set by dm at dc creation. */
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struct dc_config {
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bool gpu_vm_support;
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bool disable_disp_pll_sharing;
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};
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enum dcc_option {
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DCC_ENABLE = 0,
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DCC_DISABLE = 1,
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DCC_HALF_REQ_DISALBE = 2,
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};
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enum pipe_split_policy {
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MPC_SPLIT_DYNAMIC = 0,
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MPC_SPLIT_AVOID = 1,
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MPC_SPLIT_AVOID_MULT_DISP = 2,
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};
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enum wm_report_mode {
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WM_REPORT_DEFAULT = 0,
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WM_REPORT_OVERRIDE = 1,
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};
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struct dc_debug {
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bool surface_visual_confirm;
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bool sanity_checks;
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bool max_disp_clk;
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bool surface_trace;
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bool timing_trace;
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bool clock_trace;
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bool validation_trace;
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/* stutter efficiency related */
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bool disable_stutter;
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bool use_max_lb;
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enum dcc_option disable_dcc;
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enum pipe_split_policy pipe_split_policy;
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bool force_single_disp_pipe_split;
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bool voltage_align_fclk;
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bool disable_dfs_bypass;
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bool disable_dpp_power_gate;
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bool disable_hubp_power_gate;
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bool disable_pplib_wm_range;
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enum wm_report_mode pplib_wm_report_mode;
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unsigned int min_disp_clk_khz;
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int sr_exit_time_dpm0_ns;
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int sr_enter_plus_exit_time_dpm0_ns;
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int sr_exit_time_ns;
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int sr_enter_plus_exit_time_ns;
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int urgent_latency_ns;
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int percent_of_ideal_drambw;
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int dram_clock_change_latency_ns;
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int always_scale;
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bool disable_pplib_clock_request;
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bool disable_clock_gate;
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bool disable_dmcu;
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bool disable_psr;
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bool force_abm_enable;
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bool disable_hbup_pg;
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bool disable_dpp_pg;
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bool disable_stereo_support;
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bool vsr_support;
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bool performance_trace;
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};
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struct dc_state;
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struct resource_pool;
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struct dce_hwseq;
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struct dc {
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struct dc_caps caps;
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struct dc_cap_funcs cap_funcs;
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struct dc_stream_state_funcs stream_funcs;
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struct dc_link_funcs link_funcs;
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struct dc_config config;
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struct dc_debug debug;
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struct dc_context *ctx;
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uint8_t link_count;
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struct dc_link *links[MAX_PIPES * 2];
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struct dc_state *current_state;
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struct resource_pool *res_pool;
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/* Display Engine Clock levels */
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struct dm_pp_clock_levels sclk_lvls;
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/* Inputs into BW and WM calculations. */
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struct bw_calcs_dceip *bw_dceip;
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struct bw_calcs_vbios *bw_vbios;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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struct dcn_soc_bounding_box *dcn_soc;
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struct dcn_ip_params *dcn_ip;
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struct display_mode_lib dml;
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#endif
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/* HW functions */
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struct hw_sequencer_funcs hwss;
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struct dce_hwseq *hwseq;
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/* temp store of dm_pp_display_configuration
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* to compare to see if display config changed
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*/
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struct dm_pp_display_configuration prev_display_config;
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/* FBC compressor */
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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struct compressor *fbc_compressor;
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#endif
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};
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enum frame_buffer_mode {
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FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
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FRAME_BUFFER_MODE_ZFB_ONLY,
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FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
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} ;
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struct dchub_init_data {
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int64_t zfb_phys_addr_base;
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int64_t zfb_mc_base_addr;
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uint64_t zfb_size_in_byte;
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enum frame_buffer_mode fb_mode;
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bool dchub_initialzied;
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bool dchub_info_valid;
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};
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struct dc_init_data {
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struct hw_asic_id asic_id;
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void *driver; /* ctx */
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struct cgs_device *cgs_device;
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int num_virtual_links;
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/*
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* If 'vbios_override' not NULL, it will be called instead
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* of the real VBIOS. Intended use is Diagnostics on FPGA.
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*/
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struct dc_bios *vbios_override;
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enum dce_environment dce_environment;
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struct dc_config flags;
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uint32_t log_mask;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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uint64_t fbc_gpu_addr;
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#endif
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};
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struct dc *dc_create(const struct dc_init_data *init_params);
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void dc_destroy(struct dc **dc);
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/*******************************************************************************
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* Surface Interfaces
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******************************************************************************/
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enum {
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TRANSFER_FUNC_POINTS = 1025
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};
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// Moved here from color module for linux
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enum color_transfer_func {
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transfer_func_unknown,
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transfer_func_srgb,
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transfer_func_bt709,
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transfer_func_pq2084,
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transfer_func_pq2084_interim,
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transfer_func_linear_0_1,
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transfer_func_linear_0_125,
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transfer_func_dolbyvision,
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transfer_func_gamma_22,
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transfer_func_gamma_26
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};
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enum color_color_space {
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color_space_unsupported,
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color_space_srgb,
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color_space_bt601,
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color_space_bt709,
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color_space_xv_ycc_bt601,
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color_space_xv_ycc_bt709,
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color_space_xr_rgb,
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color_space_bt2020,
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color_space_adobe,
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color_space_dci_p3,
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color_space_sc_rgb_ms_ref,
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color_space_display_native,
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color_space_app_ctrl,
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color_space_dolby_vision,
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color_space_custom_coordinates
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};
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struct dc_hdr_static_metadata {
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/* display chromaticities and white point in units of 0.00001 */
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unsigned int chromaticity_green_x;
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unsigned int chromaticity_green_y;
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unsigned int chromaticity_blue_x;
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unsigned int chromaticity_blue_y;
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unsigned int chromaticity_red_x;
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unsigned int chromaticity_red_y;
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unsigned int chromaticity_white_point_x;
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unsigned int chromaticity_white_point_y;
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uint32_t min_luminance;
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uint32_t max_luminance;
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uint32_t maximum_content_light_level;
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uint32_t maximum_frame_average_light_level;
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bool hdr_supported;
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bool is_hdr;
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};
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enum dc_transfer_func_type {
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TF_TYPE_PREDEFINED,
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TF_TYPE_DISTRIBUTED_POINTS,
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TF_TYPE_BYPASS
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};
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||
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struct dc_transfer_func_distributed_points {
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struct fixed31_32 red[TRANSFER_FUNC_POINTS];
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||
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struct fixed31_32 green[TRANSFER_FUNC_POINTS];
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||
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struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
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||
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uint16_t end_exponent;
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||
|
|
uint16_t x_point_at_y1_red;
|
||
|
|
uint16_t x_point_at_y1_green;
|
||
|
|
uint16_t x_point_at_y1_blue;
|
||
|
|
};
|
||
|
|
|
||
|
|
enum dc_transfer_func_predefined {
|
||
|
|
TRANSFER_FUNCTION_SRGB,
|
||
|
|
TRANSFER_FUNCTION_BT709,
|
||
|
|
TRANSFER_FUNCTION_PQ,
|
||
|
|
TRANSFER_FUNCTION_LINEAR,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_transfer_func {
|
||
|
|
struct kref refcount;
|
||
|
|
struct dc_transfer_func_distributed_points tf_pts;
|
||
|
|
enum dc_transfer_func_type type;
|
||
|
|
enum dc_transfer_func_predefined tf;
|
||
|
|
struct dc_context *ctx;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This structure is filled in by dc_surface_get_status and contains
|
||
|
|
* the last requested address and the currently active address so the called
|
||
|
|
* can determine if there are any outstanding flips
|
||
|
|
*/
|
||
|
|
struct dc_plane_status {
|
||
|
|
struct dc_plane_address requested_address;
|
||
|
|
struct dc_plane_address current_address;
|
||
|
|
bool is_flip_pending;
|
||
|
|
bool is_right_eye;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_plane_state {
|
||
|
|
struct dc_plane_address address;
|
||
|
|
struct scaling_taps scaling_quality;
|
||
|
|
struct rect src_rect;
|
||
|
|
struct rect dst_rect;
|
||
|
|
struct rect clip_rect;
|
||
|
|
|
||
|
|
union plane_size plane_size;
|
||
|
|
union dc_tiling_info tiling_info;
|
||
|
|
|
||
|
|
struct dc_plane_dcc_param dcc;
|
||
|
|
struct dc_hdr_static_metadata hdr_static_ctx;
|
||
|
|
|
||
|
|
struct dc_gamma *gamma_correction;
|
||
|
|
struct dc_transfer_func *in_transfer_func;
|
||
|
|
|
||
|
|
// sourceContentAttribute cache
|
||
|
|
bool is_source_input_valid;
|
||
|
|
struct dc_hdr_static_metadata source_input_mastering_info;
|
||
|
|
enum color_color_space source_input_color_space;
|
||
|
|
enum color_transfer_func source_input_tf;
|
||
|
|
|
||
|
|
enum dc_color_space color_space;
|
||
|
|
enum surface_pixel_format format;
|
||
|
|
enum dc_rotation_angle rotation;
|
||
|
|
enum plane_stereo_format stereo_format;
|
||
|
|
|
||
|
|
bool per_pixel_alpha;
|
||
|
|
bool visible;
|
||
|
|
bool flip_immediate;
|
||
|
|
bool horizontal_mirror;
|
||
|
|
|
||
|
|
/* private to DC core */
|
||
|
|
struct dc_plane_status status;
|
||
|
|
struct dc_context *ctx;
|
||
|
|
|
||
|
|
/* private to dc_surface.c */
|
||
|
|
enum dc_irq_source irq_source;
|
||
|
|
struct kref refcount;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_plane_info {
|
||
|
|
union plane_size plane_size;
|
||
|
|
union dc_tiling_info tiling_info;
|
||
|
|
struct dc_plane_dcc_param dcc;
|
||
|
|
enum surface_pixel_format format;
|
||
|
|
enum dc_rotation_angle rotation;
|
||
|
|
enum plane_stereo_format stereo_format;
|
||
|
|
enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
|
||
|
|
bool horizontal_mirror;
|
||
|
|
bool visible;
|
||
|
|
bool per_pixel_alpha;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_scaling_info {
|
||
|
|
struct rect src_rect;
|
||
|
|
struct rect dst_rect;
|
||
|
|
struct rect clip_rect;
|
||
|
|
struct scaling_taps scaling_quality;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_surface_update {
|
||
|
|
struct dc_plane_state *surface;
|
||
|
|
|
||
|
|
/* isr safe update parameters. null means no updates */
|
||
|
|
struct dc_flip_addrs *flip_addr;
|
||
|
|
struct dc_plane_info *plane_info;
|
||
|
|
struct dc_scaling_info *scaling_info;
|
||
|
|
/* following updates require alloc/sleep/spin that is not isr safe,
|
||
|
|
* null means no updates
|
||
|
|
*/
|
||
|
|
/* gamma TO BE REMOVED */
|
||
|
|
struct dc_gamma *gamma;
|
||
|
|
struct dc_transfer_func *in_transfer_func;
|
||
|
|
struct dc_hdr_static_metadata *hdr_static_metadata;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Create a new surface with default parameters;
|
||
|
|
*/
|
||
|
|
struct dc_plane_state *dc_create_plane_state(struct dc *dc);
|
||
|
|
const struct dc_plane_status *dc_plane_get_status(
|
||
|
|
const struct dc_plane_state *plane_state);
|
||
|
|
|
||
|
|
void dc_plane_state_retain(struct dc_plane_state *plane_state);
|
||
|
|
void dc_plane_state_release(struct dc_plane_state *plane_state);
|
||
|
|
|
||
|
|
void dc_gamma_retain(struct dc_gamma *dc_gamma);
|
||
|
|
void dc_gamma_release(struct dc_gamma **dc_gamma);
|
||
|
|
struct dc_gamma *dc_create_gamma(void);
|
||
|
|
|
||
|
|
void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
|
||
|
|
void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
|
||
|
|
struct dc_transfer_func *dc_create_transfer_func(void);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This structure holds a surface address. There could be multiple addresses
|
||
|
|
* in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
|
||
|
|
* as frame durations and DCC format can also be set.
|
||
|
|
*/
|
||
|
|
struct dc_flip_addrs {
|
||
|
|
struct dc_plane_address address;
|
||
|
|
bool flip_immediate;
|
||
|
|
/* TODO: add flip duration for FreeSync */
|
||
|
|
};
|
||
|
|
|
||
|
|
bool dc_post_update_surfaces_to_stream(
|
||
|
|
struct dc *dc);
|
||
|
|
|
||
|
|
/* Surface update type is used by dc_update_surfaces_and_stream
|
||
|
|
* The update type is determined at the very beginning of the function based
|
||
|
|
* on parameters passed in and decides how much programming (or updating) is
|
||
|
|
* going to be done during the call.
|
||
|
|
*
|
||
|
|
* UPDATE_TYPE_FAST is used for really fast updates that do not require much
|
||
|
|
* logical calculations or hardware register programming. This update MUST be
|
||
|
|
* ISR safe on windows. Currently fast update will only be used to flip surface
|
||
|
|
* address.
|
||
|
|
*
|
||
|
|
* UPDATE_TYPE_MED is used for slower updates which require significant hw
|
||
|
|
* re-programming however do not affect bandwidth consumption or clock
|
||
|
|
* requirements. At present, this is the level at which front end updates
|
||
|
|
* that do not require us to run bw_calcs happen. These are in/out transfer func
|
||
|
|
* updates, viewport offset changes, recout size changes and pixel depth changes.
|
||
|
|
* This update can be done at ISR, but we want to minimize how often this happens.
|
||
|
|
*
|
||
|
|
* UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
|
||
|
|
* bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
|
||
|
|
* end related. Any time viewport dimensions, recout dimensions, scaling ratios or
|
||
|
|
* gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
|
||
|
|
* a full update. This cannot be done at ISR level and should be a rare event.
|
||
|
|
* Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
|
||
|
|
* underscan we don't expect to see this call at all.
|
||
|
|
*/
|
||
|
|
|
||
|
|
enum surface_update_type {
|
||
|
|
UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
|
||
|
|
UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
|
||
|
|
UPDATE_TYPE_FULL, /* may need to shuffle resources */
|
||
|
|
};
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Stream Interfaces
|
||
|
|
******************************************************************************/
|
||
|
|
|
||
|
|
struct dc_stream_status {
|
||
|
|
int primary_otg_inst;
|
||
|
|
int stream_enc_inst;
|
||
|
|
int plane_count;
|
||
|
|
struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
|
||
|
|
|
||
|
|
/*
|
||
|
|
* link this stream passes through
|
||
|
|
*/
|
||
|
|
struct dc_link *link;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_stream_state {
|
||
|
|
struct dc_sink *sink;
|
||
|
|
struct dc_crtc_timing timing;
|
||
|
|
|
||
|
|
struct rect src; /* composition area */
|
||
|
|
struct rect dst; /* stream addressable area */
|
||
|
|
|
||
|
|
struct audio_info audio_info;
|
||
|
|
|
||
|
|
struct freesync_context freesync_ctx;
|
||
|
|
|
||
|
|
struct dc_transfer_func *out_transfer_func;
|
||
|
|
struct colorspace_transform gamut_remap_matrix;
|
||
|
|
struct csc_transform csc_color_matrix;
|
||
|
|
|
||
|
|
enum signal_type output_signal;
|
||
|
|
|
||
|
|
enum dc_color_space output_color_space;
|
||
|
|
enum dc_dither_option dither_option;
|
||
|
|
|
||
|
|
enum view_3d_format view_format;
|
||
|
|
|
||
|
|
bool ignore_msa_timing_param;
|
||
|
|
/* TODO: custom INFO packets */
|
||
|
|
/* TODO: ABM info (DMCU) */
|
||
|
|
/* TODO: PSR info */
|
||
|
|
/* TODO: CEA VIC */
|
||
|
|
|
||
|
|
/* from core_stream struct */
|
||
|
|
struct dc_context *ctx;
|
||
|
|
|
||
|
|
/* used by DCP and FMT */
|
||
|
|
struct bit_depth_reduction_params bit_depth_params;
|
||
|
|
struct clamping_and_pixel_encoding_params clamping;
|
||
|
|
|
||
|
|
int phy_pix_clk;
|
||
|
|
enum signal_type signal;
|
||
|
|
bool dpms_off;
|
||
|
|
|
||
|
|
struct dc_stream_status status;
|
||
|
|
|
||
|
|
struct dc_cursor_attributes cursor_attributes;
|
||
|
|
|
||
|
|
/* from stream struct */
|
||
|
|
struct kref refcount;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_stream_update {
|
||
|
|
struct rect src;
|
||
|
|
struct rect dst;
|
||
|
|
struct dc_transfer_func *out_transfer_func;
|
||
|
|
};
|
||
|
|
|
||
|
|
bool dc_is_stream_unchanged(
|
||
|
|
struct dc_stream_state *old_stream, struct dc_stream_state *stream);
|
||
|
|
bool dc_is_stream_scaling_unchanged(
|
||
|
|
struct dc_stream_state *old_stream, struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set up surface attributes and associate to a stream
|
||
|
|
* The surfaces parameter is an absolute set of all surface active for the stream.
|
||
|
|
* If no surfaces are provided, the stream will be blanked; no memory read.
|
||
|
|
* Any flip related attribute changes must be done through this interface.
|
||
|
|
*
|
||
|
|
* After this call:
|
||
|
|
* Surfaces attributes are programmed and configured to be composed into stream.
|
||
|
|
* This does not trigger a flip. No surface address is programmed.
|
||
|
|
*/
|
||
|
|
|
||
|
|
bool dc_commit_planes_to_stream(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_plane_state **plane_states,
|
||
|
|
uint8_t new_plane_count,
|
||
|
|
struct dc_stream_state *dc_stream,
|
||
|
|
struct dc_state *state);
|
||
|
|
|
||
|
|
void dc_commit_updates_for_stream(struct dc *dc,
|
||
|
|
struct dc_surface_update *srf_updates,
|
||
|
|
int surface_count,
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
struct dc_stream_update *stream_update,
|
||
|
|
struct dc_plane_state **plane_states,
|
||
|
|
struct dc_state *state);
|
||
|
|
/*
|
||
|
|
* Log the current stream state.
|
||
|
|
*/
|
||
|
|
void dc_stream_log(
|
||
|
|
const struct dc_stream_state *stream,
|
||
|
|
struct dal_logger *dc_logger,
|
||
|
|
enum dc_log_type log_type);
|
||
|
|
|
||
|
|
uint8_t dc_get_current_stream_count(struct dc *dc);
|
||
|
|
struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Return the current frame counter.
|
||
|
|
*/
|
||
|
|
uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
/* TODO: Return parsed values rather than direct register read
|
||
|
|
* This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
|
||
|
|
* being refactored properly to be dce-specific
|
||
|
|
*/
|
||
|
|
bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
|
||
|
|
uint32_t *v_blank_start,
|
||
|
|
uint32_t *v_blank_end,
|
||
|
|
uint32_t *h_position,
|
||
|
|
uint32_t *v_position);
|
||
|
|
|
||
|
|
enum dc_status dc_add_stream_to_ctx(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_state *new_ctx,
|
||
|
|
struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
enum dc_status dc_remove_stream_from_ctx(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_state *new_ctx,
|
||
|
|
struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
|
||
|
|
bool dc_add_plane_to_context(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
struct dc_plane_state *plane_state,
|
||
|
|
struct dc_state *context);
|
||
|
|
|
||
|
|
bool dc_remove_plane_from_context(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
struct dc_plane_state *plane_state,
|
||
|
|
struct dc_state *context);
|
||
|
|
|
||
|
|
bool dc_rem_all_planes_for_stream(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
struct dc_state *context);
|
||
|
|
|
||
|
|
bool dc_add_all_planes_for_stream(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
struct dc_plane_state * const *plane_states,
|
||
|
|
int plane_count,
|
||
|
|
struct dc_state *context);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Structure to store surface/stream associations for validation
|
||
|
|
*/
|
||
|
|
struct dc_validation_set {
|
||
|
|
struct dc_stream_state *stream;
|
||
|
|
struct dc_plane_state *plane_states[MAX_SURFACES];
|
||
|
|
uint8_t plane_count;
|
||
|
|
};
|
||
|
|
|
||
|
|
enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
|
||
|
|
|
||
|
|
enum dc_status dc_validate_global_state(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_state *new_ctx);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function takes a stream and checks if it is guaranteed to be supported.
|
||
|
|
* Guaranteed means that MAX_COFUNC similar streams are supported.
|
||
|
|
*
|
||
|
|
* After this call:
|
||
|
|
* No hardware is programmed for call. Only validation is done.
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
void dc_resource_state_construct(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_state *dst_ctx);
|
||
|
|
|
||
|
|
void dc_resource_state_copy_construct(
|
||
|
|
const struct dc_state *src_ctx,
|
||
|
|
struct dc_state *dst_ctx);
|
||
|
|
|
||
|
|
void dc_resource_state_copy_construct_current(
|
||
|
|
const struct dc *dc,
|
||
|
|
struct dc_state *dst_ctx);
|
||
|
|
|
||
|
|
void dc_resource_state_destruct(struct dc_state *context);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* TODO update to make it about validation sets
|
||
|
|
* Set up streams and links associated to drive sinks
|
||
|
|
* The streams parameter is an absolute set of all active streams.
|
||
|
|
*
|
||
|
|
* After this call:
|
||
|
|
* Phy, Encoder, Timing Generator are programmed and enabled.
|
||
|
|
* New streams are enabled with blank stream; no memory read.
|
||
|
|
*/
|
||
|
|
bool dc_commit_state(struct dc *dc, struct dc_state *context);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set up streams and links associated to drive sinks
|
||
|
|
* The streams parameter is an absolute set of all active streams.
|
||
|
|
*
|
||
|
|
* After this call:
|
||
|
|
* Phy, Encoder, Timing Generator are programmed and enabled.
|
||
|
|
* New streams are enabled with blank stream; no memory read.
|
||
|
|
*/
|
||
|
|
/*
|
||
|
|
* Enable stereo when commit_streams is not required,
|
||
|
|
* for example, frame alternate.
|
||
|
|
*/
|
||
|
|
bool dc_enable_stereo(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_state *context,
|
||
|
|
struct dc_stream_state *streams[],
|
||
|
|
uint8_t stream_count);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Create a new default stream for the requested sink
|
||
|
|
*/
|
||
|
|
struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
|
||
|
|
|
||
|
|
void dc_stream_retain(struct dc_stream_state *dc_stream);
|
||
|
|
void dc_stream_release(struct dc_stream_state *dc_stream);
|
||
|
|
|
||
|
|
struct dc_stream_status *dc_stream_get_status(
|
||
|
|
struct dc_stream_state *dc_stream);
|
||
|
|
|
||
|
|
enum surface_update_type dc_check_update_surfaces_for_stream(
|
||
|
|
struct dc *dc,
|
||
|
|
struct dc_surface_update *updates,
|
||
|
|
int surface_count,
|
||
|
|
struct dc_stream_update *stream_update,
|
||
|
|
const struct dc_stream_status *stream_status);
|
||
|
|
|
||
|
|
|
||
|
|
struct dc_state *dc_create_state(void);
|
||
|
|
void dc_retain_state(struct dc_state *context);
|
||
|
|
void dc_release_state(struct dc_state *context);
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Link Interfaces
|
||
|
|
******************************************************************************/
|
||
|
|
|
||
|
|
struct dpcd_caps {
|
||
|
|
union dpcd_rev dpcd_rev;
|
||
|
|
union max_lane_count max_ln_count;
|
||
|
|
union max_down_spread max_down_spread;
|
||
|
|
|
||
|
|
/* dongle type (DP converter, CV smart dongle) */
|
||
|
|
enum display_dongle_type dongle_type;
|
||
|
|
/* Dongle's downstream count. */
|
||
|
|
union sink_count sink_count;
|
||
|
|
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
|
||
|
|
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
|
||
|
|
struct dc_dongle_caps dongle_caps;
|
||
|
|
|
||
|
|
uint32_t sink_dev_id;
|
||
|
|
uint32_t branch_dev_id;
|
||
|
|
int8_t branch_dev_name[6];
|
||
|
|
int8_t branch_hw_revision;
|
||
|
|
|
||
|
|
bool allow_invalid_MSA_timing_param;
|
||
|
|
bool panel_mode_edp;
|
||
|
|
bool dpcd_display_control_capable;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_link_status {
|
||
|
|
struct dpcd_caps *dpcd_caps;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* DP MST stream allocation (payload bandwidth number) */
|
||
|
|
struct link_mst_stream_allocation {
|
||
|
|
/* DIG front */
|
||
|
|
const struct stream_encoder *stream_enc;
|
||
|
|
/* associate DRM payload table with DC stream encoder */
|
||
|
|
uint8_t vcp_id;
|
||
|
|
/* number of slots required for the DP stream in transport packet */
|
||
|
|
uint8_t slot_count;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* DP MST stream allocation table */
|
||
|
|
struct link_mst_stream_allocation_table {
|
||
|
|
/* number of DP video streams */
|
||
|
|
int stream_count;
|
||
|
|
/* array of stream allocations */
|
||
|
|
struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* A link contains one or more sinks and their connected status.
|
||
|
|
* The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
|
||
|
|
*/
|
||
|
|
struct dc_link {
|
||
|
|
struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
|
||
|
|
unsigned int sink_count;
|
||
|
|
struct dc_sink *local_sink;
|
||
|
|
unsigned int link_index;
|
||
|
|
enum dc_connection_type type;
|
||
|
|
enum signal_type connector_signal;
|
||
|
|
enum dc_irq_source irq_source_hpd;
|
||
|
|
enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
|
||
|
|
/* caps is the same as reported_link_cap. link_traing use
|
||
|
|
* reported_link_cap. Will clean up. TODO
|
||
|
|
*/
|
||
|
|
struct dc_link_settings reported_link_cap;
|
||
|
|
struct dc_link_settings verified_link_cap;
|
||
|
|
struct dc_link_settings cur_link_settings;
|
||
|
|
struct dc_lane_settings cur_lane_setting;
|
||
|
|
struct dc_link_settings preferred_link_setting;
|
||
|
|
|
||
|
|
uint8_t ddc_hw_inst;
|
||
|
|
|
||
|
|
uint8_t hpd_src;
|
||
|
|
|
||
|
|
uint8_t link_enc_hw_inst;
|
||
|
|
|
||
|
|
bool test_pattern_enabled;
|
||
|
|
union compliance_test_state compliance_test_state;
|
||
|
|
|
||
|
|
void *priv;
|
||
|
|
|
||
|
|
struct ddc_service *ddc;
|
||
|
|
|
||
|
|
bool aux_mode;
|
||
|
|
|
||
|
|
/* Private to DC core */
|
||
|
|
|
||
|
|
const struct dc *dc;
|
||
|
|
|
||
|
|
struct dc_context *ctx;
|
||
|
|
|
||
|
|
struct link_encoder *link_enc;
|
||
|
|
struct graphics_object_id link_id;
|
||
|
|
union ddi_channel_mapping ddi_channel_mapping;
|
||
|
|
struct connector_device_tag_info device_tag;
|
||
|
|
struct dpcd_caps dpcd_caps;
|
||
|
|
unsigned short chip_caps;
|
||
|
|
unsigned int dpcd_sink_count;
|
||
|
|
enum edp_revision edp_revision;
|
||
|
|
bool psr_enabled;
|
||
|
|
|
||
|
|
/* MST record stream using this link */
|
||
|
|
struct link_flags {
|
||
|
|
bool dp_keep_receiver_powered;
|
||
|
|
} wa_flags;
|
||
|
|
struct link_mst_stream_allocation_table mst_stream_alloc_table;
|
||
|
|
|
||
|
|
struct dc_link_status link_status;
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Return an enumerated dc_link. dc_link order is constant and determined at
|
||
|
|
* boot time. They cannot be created or destroyed.
|
||
|
|
* Use dc_get_caps() to get number of links.
|
||
|
|
*/
|
||
|
|
static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
|
||
|
|
{
|
||
|
|
return dc->links[link_index];
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set backlight level of an embedded panel (eDP, LVDS). */
|
||
|
|
bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
|
||
|
|
uint32_t frame_ramp, const struct dc_stream_state *stream);
|
||
|
|
|
||
|
|
bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
|
||
|
|
|
||
|
|
bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
|
||
|
|
|
||
|
|
bool dc_link_setup_psr(struct dc_link *dc_link,
|
||
|
|
const struct dc_stream_state *stream, struct psr_config *psr_config,
|
||
|
|
struct psr_context *psr_context);
|
||
|
|
|
||
|
|
/* Request DC to detect if there is a Panel connected.
|
||
|
|
* boot - If this call is during initial boot.
|
||
|
|
* Return false for any type of detection failure or MST detection
|
||
|
|
* true otherwise. True meaning further action is required (status update
|
||
|
|
* and OS notification).
|
||
|
|
*/
|
||
|
|
enum dc_detect_reason {
|
||
|
|
DETECT_REASON_BOOT,
|
||
|
|
DETECT_REASON_HPD,
|
||
|
|
DETECT_REASON_HPDRX,
|
||
|
|
};
|
||
|
|
|
||
|
|
bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
|
||
|
|
|
||
|
|
/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
|
||
|
|
* Return:
|
||
|
|
* true - Downstream port status changed. DM should call DC to do the
|
||
|
|
* detection.
|
||
|
|
* false - no change in Downstream port status. No further action required
|
||
|
|
* from DM. */
|
||
|
|
bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
|
||
|
|
union hpd_irq_data *hpd_irq_dpcd_data);
|
||
|
|
|
||
|
|
struct dc_sink_init_data;
|
||
|
|
|
||
|
|
struct dc_sink *dc_link_add_remote_sink(
|
||
|
|
struct dc_link *dc_link,
|
||
|
|
const uint8_t *edid,
|
||
|
|
int len,
|
||
|
|
struct dc_sink_init_data *init_data);
|
||
|
|
|
||
|
|
void dc_link_remove_remote_sink(
|
||
|
|
struct dc_link *link,
|
||
|
|
struct dc_sink *sink);
|
||
|
|
|
||
|
|
/* Used by diagnostics for virtual link at the moment */
|
||
|
|
|
||
|
|
void dc_link_dp_set_drive_settings(
|
||
|
|
struct dc_link *link,
|
||
|
|
struct link_training_settings *lt_settings);
|
||
|
|
|
||
|
|
enum link_training_result dc_link_dp_perform_link_training(
|
||
|
|
struct dc_link *link,
|
||
|
|
const struct dc_link_settings *link_setting,
|
||
|
|
bool skip_video_pattern);
|
||
|
|
|
||
|
|
void dc_link_dp_enable_hpd(const struct dc_link *link);
|
||
|
|
|
||
|
|
void dc_link_dp_disable_hpd(const struct dc_link *link);
|
||
|
|
|
||
|
|
bool dc_link_dp_set_test_pattern(
|
||
|
|
struct dc_link *link,
|
||
|
|
enum dp_test_pattern test_pattern,
|
||
|
|
const struct link_training_settings *p_link_settings,
|
||
|
|
const unsigned char *p_custom_pattern,
|
||
|
|
unsigned int cust_pattern_size);
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Sink Interfaces - A sink corresponds to a display output device
|
||
|
|
******************************************************************************/
|
||
|
|
|
||
|
|
struct dc_container_id {
|
||
|
|
// 128bit GUID in binary form
|
||
|
|
unsigned char guid[16];
|
||
|
|
// 8 byte port ID -> ELD.PortID
|
||
|
|
unsigned int portId[2];
|
||
|
|
// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
|
||
|
|
unsigned short manufacturerName;
|
||
|
|
// 2 byte product code -> ELD.ProductCode
|
||
|
|
unsigned short productCode;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The sink structure contains EDID and other display device properties
|
||
|
|
*/
|
||
|
|
struct dc_sink {
|
||
|
|
enum signal_type sink_signal;
|
||
|
|
struct dc_edid dc_edid; /* raw edid */
|
||
|
|
struct dc_edid_caps edid_caps; /* parse display caps */
|
||
|
|
struct dc_container_id *dc_container_id;
|
||
|
|
uint32_t dongle_max_pix_clk;
|
||
|
|
void *priv;
|
||
|
|
struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
|
||
|
|
bool converter_disable_audio;
|
||
|
|
|
||
|
|
/* private to DC core */
|
||
|
|
struct dc_link *link;
|
||
|
|
struct dc_context *ctx;
|
||
|
|
|
||
|
|
/* private to dc_sink.c */
|
||
|
|
struct kref refcount;
|
||
|
|
};
|
||
|
|
|
||
|
|
void dc_sink_retain(struct dc_sink *sink);
|
||
|
|
void dc_sink_release(struct dc_sink *sink);
|
||
|
|
|
||
|
|
struct dc_sink_init_data {
|
||
|
|
enum signal_type sink_signal;
|
||
|
|
struct dc_link *link;
|
||
|
|
uint32_t dongle_max_pix_clk;
|
||
|
|
bool converter_disable_audio;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Cursor interfaces - To manages the cursor within a stream
|
||
|
|
******************************************************************************/
|
||
|
|
/* TODO: Deprecated once we switch to dc_set_cursor_position */
|
||
|
|
bool dc_stream_set_cursor_attributes(
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
const struct dc_cursor_attributes *attributes);
|
||
|
|
|
||
|
|
bool dc_stream_set_cursor_position(
|
||
|
|
struct dc_stream_state *stream,
|
||
|
|
const struct dc_cursor_position *position);
|
||
|
|
|
||
|
|
/* Newer interfaces */
|
||
|
|
struct dc_cursor {
|
||
|
|
struct dc_plane_address address;
|
||
|
|
struct dc_cursor_attributes attributes;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Interrupt interfaces
|
||
|
|
******************************************************************************/
|
||
|
|
enum dc_irq_source dc_interrupt_to_irq_source(
|
||
|
|
struct dc *dc,
|
||
|
|
uint32_t src_id,
|
||
|
|
uint32_t ext_id);
|
||
|
|
void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
|
||
|
|
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
|
||
|
|
enum dc_irq_source dc_get_hpd_irq_source_at_index(
|
||
|
|
struct dc *dc, uint32_t link_index);
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Power Interfaces
|
||
|
|
******************************************************************************/
|
||
|
|
|
||
|
|
void dc_set_power_state(
|
||
|
|
struct dc *dc,
|
||
|
|
enum dc_acpi_cm_power_state power_state);
|
||
|
|
void dc_resume(struct dc *dc);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* DPCD access interfaces
|
||
|
|
*/
|
||
|
|
|
||
|
|
bool dc_submit_i2c(
|
||
|
|
struct dc *dc,
|
||
|
|
uint32_t link_index,
|
||
|
|
struct i2c_command *cmd);
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* DC_INTERFACE_H_ */
|