339 lines
9.4 KiB
C
339 lines
9.4 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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/*
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* GPU scratch registers helpers function.
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*/
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/**
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* amdgpu_gfx_scratch_get - Allocate a scratch register
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*
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* @adev: amdgpu_device pointer
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* @reg: scratch register mmio offset
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*
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* Allocate a CP scratch register for use by the driver (all asics).
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* Returns 0 on success or -EINVAL on failure.
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*/
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int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
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{
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int i;
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i = ffs(adev->gfx.scratch.free_mask);
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if (i != 0 && i <= adev->gfx.scratch.num_reg) {
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i--;
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adev->gfx.scratch.free_mask &= ~(1u << i);
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*reg = adev->gfx.scratch.reg_base + i;
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return 0;
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}
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return -EINVAL;
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}
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/**
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* amdgpu_gfx_scratch_free - Free a scratch register
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*
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* @adev: amdgpu_device pointer
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* @reg: scratch register mmio offset
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*
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* Free a CP scratch register allocated for use by the driver (all asics)
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*/
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void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
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{
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adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
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}
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/**
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* amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
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*
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* @mask: array in which the per-shader array disable masks will be stored
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* @max_se: number of SEs
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* @max_sh: number of SHs
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*
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* The bitmask of CUs to be disabled in the shader array determined by se and
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* sh is stored in mask[se * max_sh + sh].
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*/
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void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
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{
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unsigned se, sh, cu;
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const char *p;
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memset(mask, 0, sizeof(*mask) * max_se * max_sh);
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if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
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return;
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p = amdgpu_disable_cu;
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for (;;) {
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char *next;
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int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
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if (ret < 3) {
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DRM_ERROR("amdgpu: could not parse disable_cu\n");
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return;
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}
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if (se < max_se && sh < max_sh && cu < 16) {
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DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
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mask[se * max_sh + sh] |= 1u << cu;
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} else {
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DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
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se, sh, cu);
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}
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next = strchr(p, ',');
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if (!next)
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break;
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p = next + 1;
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}
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}
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static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
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{
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if (amdgpu_compute_multipipe != -1) {
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DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
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amdgpu_compute_multipipe);
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return amdgpu_compute_multipipe == 1;
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}
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/* FIXME: spreading the queues across pipes causes perf regressions
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* on POLARIS11 compute workloads */
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if (adev->asic_type == CHIP_POLARIS11)
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return false;
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return adev->gfx.mec.num_mec > 1;
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}
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void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
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{
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int i, queue, pipe, mec;
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bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
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/* policy for amdgpu compute queue ownership */
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for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
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queue = i % adev->gfx.mec.num_queue_per_pipe;
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pipe = (i / adev->gfx.mec.num_queue_per_pipe)
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% adev->gfx.mec.num_pipe_per_mec;
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mec = (i / adev->gfx.mec.num_queue_per_pipe)
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/ adev->gfx.mec.num_pipe_per_mec;
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/* we've run out of HW */
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if (mec >= adev->gfx.mec.num_mec)
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break;
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if (multipipe_policy) {
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/* policy: amdgpu owns the first two queues of the first MEC */
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if (mec == 0 && queue < 2)
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set_bit(i, adev->gfx.mec.queue_bitmap);
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} else {
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/* policy: amdgpu owns all queues in the first pipe */
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if (mec == 0 && pipe == 0)
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set_bit(i, adev->gfx.mec.queue_bitmap);
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}
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}
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/* update the number of active compute rings */
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adev->gfx.num_compute_rings =
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bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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/* If you hit this case and edited the policy, you probably just
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* need to increase AMDGPU_MAX_COMPUTE_RINGS */
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if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS))
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adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
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}
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static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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int queue_bit;
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int mec, pipe, queue;
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queue_bit = adev->gfx.mec.num_mec
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* adev->gfx.mec.num_pipe_per_mec
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* adev->gfx.mec.num_queue_per_pipe;
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while (queue_bit-- >= 0) {
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if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
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continue;
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amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
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/* Using pipes 2/3 from MEC 2 seems cause problems */
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if (mec == 1 && pipe > 1)
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continue;
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ring->me = mec + 1;
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ring->pipe = pipe;
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ring->queue = queue;
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return 0;
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}
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dev_err(adev->dev, "Failed to find a queue for KIQ\n");
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return -EINVAL;
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}
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int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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int r = 0;
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spin_lock_init(&kiq->ring_lock);
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r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
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if (r)
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return r;
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ring->adev = NULL;
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ring->ring_obj = NULL;
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ring->use_doorbell = true;
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ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
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r = amdgpu_gfx_kiq_acquire(adev, ring);
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if (r)
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return r;
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ring->eop_gpu_addr = kiq->eop_gpu_addr;
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sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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r = amdgpu_ring_init(adev, ring, 1024,
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irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
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if (r)
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dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
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return r;
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}
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void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq)
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{
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amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
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amdgpu_ring_fini(ring);
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}
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void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
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}
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int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
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unsigned hpd_size)
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{
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int r;
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u32 *hpd;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
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&kiq->eop_gpu_addr, (void **)&hpd);
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if (r) {
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dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
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return r;
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}
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memset(hpd, 0, hpd_size);
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r = amdgpu_bo_reserve(kiq->eop_obj, true);
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if (unlikely(r != 0))
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dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
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amdgpu_bo_kunmap(kiq->eop_obj);
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amdgpu_bo_unreserve(kiq->eop_obj);
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return 0;
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}
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/* create MQD for each compute queue */
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int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
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unsigned mqd_size)
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{
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struct amdgpu_ring *ring = NULL;
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int r, i;
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/* create MQD for KIQ */
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ring = &adev->gfx.kiq.ring;
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if (!ring->mqd_obj) {
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/* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
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* otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
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* deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
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* KIQ MQD no matter SRIOV or Bare-metal
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*/
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r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
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&ring->mqd_gpu_addr, &ring->mqd_ptr);
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if (r) {
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dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
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return r;
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}
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/* prepare MQD backup */
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adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
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if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
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dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
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}
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/* create MQD for each KCQ */
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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if (!ring->mqd_obj) {
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r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
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&ring->mqd_gpu_addr, &ring->mqd_ptr);
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if (r) {
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dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
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return r;
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}
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/* prepare MQD backup */
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adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
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if (!adev->gfx.mec.mqd_backup[i])
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dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
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}
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}
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return 0;
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}
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void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = NULL;
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int i;
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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kfree(adev->gfx.mec.mqd_backup[i]);
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amdgpu_bo_free_kernel(&ring->mqd_obj,
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&ring->mqd_gpu_addr,
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&ring->mqd_ptr);
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}
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ring = &adev->gfx.kiq.ring;
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kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
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amdgpu_bo_free_kernel(&ring->mqd_obj,
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&ring->mqd_gpu_addr,
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&ring->mqd_ptr);
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}
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