281 lines
7.7 KiB
C
281 lines
7.7 KiB
C
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/uaccess.h>
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#include <hv/drv_pcie_rc_intf.h>
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#include <arch/spr_def.h>
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#include <asm/traps.h>
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#include <linux/perf_event.h>
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/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
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#define IS_HW_CLEARED 1
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/*
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* The set of interrupts we enable for arch_local_irq_enable().
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* This is initialized to have just a single interrupt that the kernel
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* doesn't actually use as a sentinel. During kernel init,
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* interrupts are added as the kernel gets prepared to support them.
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* NOTE: we could probably initialize them all statically up front.
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*/
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DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
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INITIAL_INTERRUPTS_ENABLED;
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EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);
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/* Define per-tile device interrupt statistics state. */
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DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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/*
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* Define per-tile irq disable mask; the hardware/HV only has a single
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* mask that we use to implement both masking and disabling.
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*/
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static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
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____cacheline_internodealigned_in_smp;
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/*
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* Per-tile IRQ nesting depth. Used to make sure we enable newly
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* enabled IRQs before exiting the outermost interrupt.
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*/
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static DEFINE_PER_CPU(int, irq_depth);
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#if CHIP_HAS_IPI()
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/* Use SPRs to manipulate device interrupts. */
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#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
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#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
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#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
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#else
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/* Use HV to manipulate device interrupts. */
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#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
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#define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
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#define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
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#endif
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/*
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* The interrupt handling path, implemented in terms of HV interrupt
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* emulation on TILEPro, and IPI hardware on TILE-Gx.
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* Entered with interrupts disabled.
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*/
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void tile_dev_intr(struct pt_regs *regs, int intnum)
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{
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int depth = __this_cpu_inc_return(irq_depth);
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unsigned long original_irqs;
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unsigned long remaining_irqs;
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struct pt_regs *old_regs;
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#if CHIP_HAS_IPI()
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/*
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* Pending interrupts are listed in an SPR. We might be
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* nested, so be sure to only handle irqs that weren't already
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* masked by a previous interrupt. Then, mask out the ones
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* we're going to handle.
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*/
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unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
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original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
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__insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
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#else
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/*
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* Hypervisor performs the equivalent of the Gx code above and
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* then puts the pending interrupt mask into a system save reg
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* for us to find.
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*/
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original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
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#endif
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remaining_irqs = original_irqs;
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/* Track time spent here in an interrupt context. */
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old_regs = set_irq_regs(regs);
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irq_enter();
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#ifdef CONFIG_DEBUG_STACKOVERFLOW
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/* Debugging check for stack overflow: less than 1/8th stack free? */
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{
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long sp = stack_pointer - (long) current_thread_info();
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if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
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pr_emerg("%s: stack overflow: %ld\n",
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__func__, sp - sizeof(struct thread_info));
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dump_stack();
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}
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}
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#endif
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while (remaining_irqs) {
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unsigned long irq = __ffs(remaining_irqs);
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remaining_irqs &= ~(1UL << irq);
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/* Count device irqs; Linux IPIs are counted elsewhere. */
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if (irq != IRQ_RESCHEDULE)
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__this_cpu_inc(irq_stat.irq_dev_intr_count);
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generic_handle_irq(irq);
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}
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/*
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* If we weren't nested, turn on all enabled interrupts,
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* including any that were reenabled during interrupt
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* handling.
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*/
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if (depth == 1)
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unmask_irqs(~__this_cpu_read(irq_disable_mask));
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__this_cpu_dec(irq_depth);
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/*
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* Track time spent against the current process again and
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* process any softirqs if they are waiting.
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*/
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irq_exit();
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set_irq_regs(old_regs);
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}
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/*
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* Remove an irq from the disabled mask. If we're in an interrupt
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* context, defer enabling the HW interrupt until we leave.
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*/
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static void tile_irq_chip_enable(struct irq_data *d)
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{
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get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq);
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if (__this_cpu_read(irq_depth) == 0)
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unmask_irqs(1UL << d->irq);
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put_cpu_var(irq_disable_mask);
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}
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/*
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* Add an irq to the disabled mask. We disable the HW interrupt
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* immediately so that there's no possibility of it firing. If we're
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* in an interrupt context, the return path is careful to avoid
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* unmasking a newly disabled interrupt.
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*/
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static void tile_irq_chip_disable(struct irq_data *d)
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{
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get_cpu_var(irq_disable_mask) |= (1UL << d->irq);
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mask_irqs(1UL << d->irq);
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put_cpu_var(irq_disable_mask);
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}
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/* Mask an interrupt. */
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static void tile_irq_chip_mask(struct irq_data *d)
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{
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mask_irqs(1UL << d->irq);
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}
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/* Unmask an interrupt. */
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static void tile_irq_chip_unmask(struct irq_data *d)
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{
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unmask_irqs(1UL << d->irq);
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}
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/*
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* Clear an interrupt before processing it so that any new assertions
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* will trigger another irq.
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*/
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static void tile_irq_chip_ack(struct irq_data *d)
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{
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if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED)
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clear_irqs(1UL << d->irq);
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}
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/*
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* For per-cpu interrupts, we need to avoid unmasking any interrupts
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* that we disabled via disable_percpu_irq().
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*/
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static void tile_irq_chip_eoi(struct irq_data *d)
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{
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if (!(__this_cpu_read(irq_disable_mask) & (1UL << d->irq)))
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unmask_irqs(1UL << d->irq);
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}
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static struct irq_chip tile_irq_chip = {
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.name = "tile_irq_chip",
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.irq_enable = tile_irq_chip_enable,
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.irq_disable = tile_irq_chip_disable,
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.irq_ack = tile_irq_chip_ack,
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.irq_eoi = tile_irq_chip_eoi,
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.irq_mask = tile_irq_chip_mask,
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.irq_unmask = tile_irq_chip_unmask,
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};
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void __init init_IRQ(void)
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{
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ipi_init();
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}
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void setup_irq_regs(void)
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{
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/* Enable interrupt delivery. */
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unmask_irqs(~0UL);
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#if CHIP_HAS_IPI()
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arch_local_irq_unmask(INT_IPI_K);
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#endif
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}
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void tile_irq_activate(unsigned int irq, int tile_irq_type)
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{
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/*
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* We use handle_level_irq() by default because the pending
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* interrupt vector (whether modeled by the HV on
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* TILEPro or implemented in hardware on TILE-Gx) has
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* level-style semantics for each bit. An interrupt fires
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* whenever a bit is high, not just at edges.
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*/
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irq_flow_handler_t handle = handle_level_irq;
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if (tile_irq_type == TILE_IRQ_PERCPU)
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handle = handle_percpu_irq;
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irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
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/*
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* Flag interrupts that are hardware-cleared so that ack()
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* won't clear them.
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*/
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if (tile_irq_type == TILE_IRQ_HW_CLEAR)
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irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
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}
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EXPORT_SYMBOL(tile_irq_activate);
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void ack_bad_irq(unsigned int irq)
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{
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pr_err("unexpected IRQ trap at vector %02x\n", irq);
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}
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/*
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* /proc/interrupts printing:
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*/
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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#ifdef CONFIG_PERF_EVENTS
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int i;
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seq_printf(p, "%*s: ", prec, "PMI");
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for_each_online_cpu(i)
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seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
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seq_puts(p, " perf_events\n");
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#endif
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return 0;
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}
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#if CHIP_HAS_IPI()
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int arch_setup_hwirq(unsigned int irq, int node)
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{
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return irq >= NR_IRQS ? -EINVAL : 0;
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}
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void arch_teardown_hwirq(unsigned int irq) { }
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#endif
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