156 lines
4.3 KiB
C
156 lines
4.3 KiB
C
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/* Flush dcache and invalidate icache when the dcache is in writeback mode
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*
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* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <asm/smp.h>
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#include "cache-smp.h"
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/**
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* flush_icache_page - Flush a page from the dcache and invalidate the icache
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* @vma: The VMA the page is part of.
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* @page: The page to be flushed.
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*
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* Write a page back from the dcache and invalidate the icache so that we can
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* run code from it that we've just written into it
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*/
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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unsigned long start = page_to_phys(page);
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unsigned long flags;
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flags = smp_lock_cache();
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mn10300_local_dcache_flush_page(start);
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mn10300_local_icache_inv_page(start);
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smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, start + PAGE_SIZE);
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smp_unlock_cache(flags);
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}
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EXPORT_SYMBOL(flush_icache_page);
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/**
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* flush_icache_page_range - Flush dcache and invalidate icache for part of a
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* single page
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* @start: The starting virtual address of the page part.
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* @end: The ending virtual address of the page part.
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*
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* Flush the dcache and invalidate the icache for part of a single page, as
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* determined by the virtual addresses given. The page must be in the paged
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* area.
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*/
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static void flush_icache_page_range(unsigned long start, unsigned long end)
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{
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unsigned long addr, size, off;
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struct page *page;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *ppte, pte;
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/* work out how much of the page to flush */
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off = start & ~PAGE_MASK;
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size = end - start;
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/* get the physical address the page is mapped to from the page
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* tables */
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pgd = pgd_offset(current->mm, start);
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if (!pgd || !pgd_val(*pgd))
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return;
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pud = pud_offset(pgd, start);
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if (!pud || !pud_val(*pud))
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return;
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pmd = pmd_offset(pud, start);
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if (!pmd || !pmd_val(*pmd))
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return;
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ppte = pte_offset_map(pmd, start);
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if (!ppte)
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return;
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pte = *ppte;
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pte_unmap(ppte);
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if (pte_none(pte))
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return;
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page = pte_page(pte);
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if (!page)
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return;
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addr = page_to_phys(page);
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/* flush the dcache and invalidate the icache coverage on that
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* region */
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mn10300_local_dcache_flush_range2(addr + off, size);
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mn10300_local_icache_inv_range2(addr + off, size);
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smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, end);
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}
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/**
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* flush_icache_range - Globally flush dcache and invalidate icache for region
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* @start: The starting virtual address of the region.
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* @end: The ending virtual address of the region.
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*
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* This is used by the kernel to globally flush some code it has just written
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* from the dcache back to RAM and then to globally invalidate the icache over
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* that region so that that code can be run on all CPUs in the system.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long start_page, end_page;
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unsigned long flags;
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flags = smp_lock_cache();
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if (end > 0x80000000UL) {
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/* addresses above 0xa0000000 do not go through the cache */
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if (end > 0xa0000000UL) {
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end = 0xa0000000UL;
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if (start >= end)
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goto done;
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}
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/* kernel addresses between 0x80000000 and 0x9fffffff do not
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* require page tables, so we just map such addresses
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* directly */
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start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;
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mn10300_local_dcache_flush_range(start_page, end);
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mn10300_local_icache_inv_range(start_page, end);
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smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end);
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if (start_page == start)
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goto done;
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end = start_page;
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}
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start_page = start & PAGE_MASK;
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end_page = (end - 1) & PAGE_MASK;
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if (start_page == end_page) {
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/* the first and last bytes are on the same page */
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flush_icache_page_range(start, end);
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} else if (start_page + 1 == end_page) {
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/* split over two virtually contiguous pages */
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flush_icache_page_range(start, end_page);
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flush_icache_page_range(end_page, end);
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} else {
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/* more than 2 pages; just flush the entire cache */
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mn10300_dcache_flush();
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mn10300_icache_inv();
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smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0);
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}
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done:
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smp_unlock_cache(flags);
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}
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EXPORT_SYMBOL(flush_icache_range);
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