213 lines
5.5 KiB
C
213 lines
5.5 KiB
C
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/*
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* Platform support for LPC32xx SoC
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/amba/pl08x.h>
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#include <linux/amba/mmci.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/mtd/lpc32xx_slc.h>
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#include <linux/mtd/lpc32xx_mlc.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <mach/board.h>
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#include "common.h"
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/*
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* AMBA LCD controller
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*/
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static struct clcd_panel conn_lcd_panel = {
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.mode = {
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.name = "QVGA portrait",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 191828,
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.left_margin = 22,
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.right_margin = 11,
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.upper_margin = 2,
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.lower_margin = 1,
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.hsync_len = 5,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = (TIM2_IVS | TIM2_IHS),
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.cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
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CNTL_LCDBPP16_565),
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.bpp = 16,
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};
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#define PANEL_SIZE (3 * SZ_64K)
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static int lpc32xx_clcd_setup(struct clcd_fb *fb)
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{
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dma_addr_t dma;
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fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, PANEL_SIZE, &dma,
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GFP_KERNEL);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map framebuffer\n");
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return -ENOMEM;
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}
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = PANEL_SIZE;
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fb->panel = &conn_lcd_panel;
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return 0;
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}
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static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
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{
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return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
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fb->fb.fix.smem_start, fb->fb.fix.smem_len);
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}
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static void lpc32xx_clcd_remove(struct clcd_fb *fb)
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{
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dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
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fb->fb.fix.smem_start);
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}
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static struct clcd_board lpc32xx_clcd_data = {
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.name = "Phytec LCD",
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.setup = lpc32xx_clcd_setup,
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.mmap = lpc32xx_clcd_mmap,
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.remove = lpc32xx_clcd_remove,
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};
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static struct pl08x_channel_data pl08x_slave_channels[] = {
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{
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.bus_id = "nand-slc",
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.min_signal = 1, /* SLC NAND Flash */
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.max_signal = 1,
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.periph_buses = PL08X_AHB1,
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},
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{
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.bus_id = "nand-mlc",
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.min_signal = 12, /* MLC NAND Flash */
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.max_signal = 12,
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.periph_buses = PL08X_AHB1,
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},
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};
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static int pl08x_get_signal(const struct pl08x_channel_data *cd)
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{
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return cd->min_signal;
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}
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static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
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{
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}
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static struct pl08x_platform_data pl08x_pd = {
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/* Some reasonable memcpy defaults */
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.memcpy_burst_size = PL08X_BURST_SZ_256,
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.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
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.slave_channels = &pl08x_slave_channels[0],
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.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
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.get_xfer_signal = pl08x_get_signal,
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.put_xfer_signal = pl08x_put_signal,
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.lli_buses = PL08X_AHB1,
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.mem_buses = PL08X_AHB1,
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};
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static struct mmci_platform_data lpc32xx_mmci_data = {
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.ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
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MMC_VDD_32_33 | MMC_VDD_33_34,
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};
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static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
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.dma_filter = pl08x_filter_id,
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};
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static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
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.dma_filter = pl08x_filter_id,
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};
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static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
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OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
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OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
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OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
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OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
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OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
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&lpc32xx_mmci_data),
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OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
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&lpc32xx_slc_data),
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OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
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&lpc32xx_mlc_data),
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{ }
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};
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static void __init lpc3250_machine_init(void)
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{
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u32 tmp;
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/* Setup LCD muxing to RGB565 */
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tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
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~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
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LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
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tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
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__raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
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lpc32xx_serial_init();
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/* Test clock needed for UDA1380 initial init */
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__raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
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LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
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LPC32XX_CLKPWR_TEST_CLK_SEL);
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of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
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}
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static const char *const lpc32xx_dt_compat[] __initconst = {
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"nxp,lpc3220",
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"nxp,lpc3230",
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"nxp,lpc3240",
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"nxp,lpc3250",
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NULL
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};
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DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
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.atag_offset = 0x100,
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.map_io = lpc32xx_map_io,
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.init_machine = lpc3250_machine_init,
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.dt_compat = lpc32xx_dt_compat,
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MACHINE_END
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