391 lines
8.5 KiB
Plaintext
391 lines
8.5 KiB
Plaintext
|
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||
|
|
/*
|
||
|
|
* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include <dt-bindings/clock/suniv-ccu.h>
|
||
|
|
#include <dt-bindings/reset/suniv-ccu.h>
|
||
|
|
|
||
|
|
/ {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
lradc: lradc@1c23400 {
|
||
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
||
|
|
reg = <0x01c23400 0x400>;
|
||
|
|
interrupts = <22>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
clocks {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
osc24M: clk-24M {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <24000000>;
|
||
|
|
clock-output-names = "osc24M";
|
||
|
|
};
|
||
|
|
|
||
|
|
osc32k: clk-32k {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <32768>;
|
||
|
|
clock-output-names = "osc32k";
|
||
|
|
};
|
||
|
|
|
||
|
|
fake100M: clk-100M {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <100000000>;
|
||
|
|
clock-output-names = "fake-100M";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
cpus {
|
||
|
|
#address-cells = <0>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
cpu {
|
||
|
|
compatible = "arm,arm926ej-s";
|
||
|
|
device_type = "cpu";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
de: display-engine {
|
||
|
|
compatible = "allwinner,suniv-display-engine";
|
||
|
|
allwinner,pipelines = <&fe0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
soc {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
sram-controller@1c00000 {
|
||
|
|
compatible = "allwinner,sun4i-a10-sram-controller";
|
||
|
|
reg = <0x01c00000 0x30>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
sram_d: sram@10000 {
|
||
|
|
compatible = "mmio-sram";
|
||
|
|
reg = <0x00010000 0x1000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x00010000 0x1000>;
|
||
|
|
|
||
|
|
otg_sram: sram-section@0 {
|
||
|
|
compatible = "allwinner,sun4i-a10-sram-d";
|
||
|
|
reg = <0x0000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi0: spi@1c05000 {
|
||
|
|
compatible = "allwinner,suniv-spi",
|
||
|
|
"allwinner,sun8i-h3-spi";
|
||
|
|
reg = <0x01c05000 0x1000>;
|
||
|
|
interrupts = <10>;
|
||
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
|
||
|
|
clock-names = "ahb", "mod";
|
||
|
|
resets = <&ccu RST_BUS_SPI0>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1: spi@1c06000 {
|
||
|
|
compatible = "allwinner,suniv-spi",
|
||
|
|
"allwinner,sun8i-h3-spi";
|
||
|
|
reg = <0x01c06000 0x1000>;
|
||
|
|
interrupts = <11>;
|
||
|
|
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
|
||
|
|
clock-names = "ahb", "mod";
|
||
|
|
resets = <&ccu RST_BUS_SPI1>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
tcon0: lcd-controller@1c0c000 {
|
||
|
|
compatible = "allwinner,suniv-tcon";
|
||
|
|
reg = <0x01c0c000 0x1000>;
|
||
|
|
interrupts = <29>;
|
||
|
|
clocks = <&ccu CLK_BUS_LCD>,
|
||
|
|
<&ccu CLK_TCON>,
|
||
|
|
<&osc24M>; /* Still unknown */
|
||
|
|
clock-names = "ahb",
|
||
|
|
"tcon-ch0",
|
||
|
|
"tcon-ch1";
|
||
|
|
clock-output-names = "tcon-pixel-clock";
|
||
|
|
resets = <&ccu RST_BUS_LCD>;
|
||
|
|
reset-names = "lcd";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
ports {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
tcon0_in: port@0 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0>;
|
||
|
|
|
||
|
|
tcon0_in_be0: endpoint@0 {
|
||
|
|
reg = <0>;
|
||
|
|
remote-endpoint = <&be0_out_tcon0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
tcon0_out: port@1 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc0: mmc@1c0f000 {
|
||
|
|
compatible = "allwinner,suniv-mmc",
|
||
|
|
"allwinner,sun7i-a20-mmc";
|
||
|
|
reg = <0x01c0f000 0x1000>;
|
||
|
|
clocks = <&ccu CLK_BUS_MMC0>,
|
||
|
|
<&ccu CLK_MMC0>,
|
||
|
|
<&ccu CLK_MMC0_OUTPUT>,
|
||
|
|
<&ccu CLK_MMC0_SAMPLE>;
|
||
|
|
clock-names = "ahb",
|
||
|
|
"mmc",
|
||
|
|
"output",
|
||
|
|
"sample";
|
||
|
|
resets = <&ccu RST_BUS_MMC0>;
|
||
|
|
reset-names = "ahb";
|
||
|
|
interrupts = <23>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&mmc0_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc1: mmc@1c10000 {
|
||
|
|
compatible = "allwinner,suniv-mmc",
|
||
|
|
"allwinner,sun7i-a20-mmc";
|
||
|
|
reg = <0x01c10000 0x1000>;
|
||
|
|
clocks = <&ccu CLK_BUS_MMC1>,
|
||
|
|
<&ccu CLK_MMC1>,
|
||
|
|
<&ccu CLK_MMC1_OUTPUT>,
|
||
|
|
<&ccu CLK_MMC1_SAMPLE>;
|
||
|
|
clock-names = "ahb",
|
||
|
|
"mmc",
|
||
|
|
"output",
|
||
|
|
"sample";
|
||
|
|
resets = <&ccu RST_BUS_MMC1>;
|
||
|
|
reset-names = "ahb";
|
||
|
|
interrupts = <24>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ccu: clock@1c20000 {
|
||
|
|
compatible = "allwinner,suniv-ccu";
|
||
|
|
reg = <0x01c20000 0x400>;
|
||
|
|
clocks = <&osc24M>, <&osc32k>;
|
||
|
|
clock-names = "hosc", "losc";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
intc: interrupt-controller@1c20400 {
|
||
|
|
compatible = "allwinner,suniv-ic";
|
||
|
|
reg = <0x01c20400 0x400>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pio: pinctrl@1c20800 {
|
||
|
|
compatible = "allwinner,suniv-pinctrl";
|
||
|
|
reg = <0x01c20800 0x400>;
|
||
|
|
interrupts = <38>, <39>, <40>;
|
||
|
|
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
|
||
|
|
clock-names = "apb", "hosc", "losc";
|
||
|
|
gpio-controller;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
#gpio-cells = <3>;
|
||
|
|
|
||
|
|
spi0_pins_a: spi0-pins-pc {
|
||
|
|
pins = "PC0", "PC1", "PC2", "PC3";
|
||
|
|
function = "spi0";
|
||
|
|
};
|
||
|
|
|
||
|
|
lcd_rgb666_pins: lcd-rgb666-pins {
|
||
|
|
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
|
||
|
|
"PD5", "PD6", "PD7", "PD8", "PD9",
|
||
|
|
"PD10", "PD11", "PD12", "PD13", "PD14",
|
||
|
|
"PD15", "PD16", "PD17", "PD18", "PD19",
|
||
|
|
"PD20", "PD21";
|
||
|
|
function = "lcd";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0_pins_a: uart-pins-pe {
|
||
|
|
pins = "PE0", "PE1";
|
||
|
|
function = "uart0";
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc0_pins: mmc0-pins {
|
||
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
||
|
|
function = "mmc0";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@1c20c00 {
|
||
|
|
compatible = "allwinner,suniv-timer";
|
||
|
|
reg = <0x01c20c00 0x90>;
|
||
|
|
interrupts = <13>;
|
||
|
|
clocks = <&osc24M>;
|
||
|
|
};
|
||
|
|
|
||
|
|
wdt: watchdog@1c20ca0 {
|
||
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
||
|
|
reg = <0x01c20ca0 0x20>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0: serial@1c25000 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c25000 0x400>;
|
||
|
|
interrupts = <1>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
||
|
|
resets = <&ccu RST_BUS_UART0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1: serial@1c25400 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c25400 0x400>;
|
||
|
|
interrupts = <2>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
||
|
|
resets = <&ccu RST_BUS_UART1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart2: serial@1c25800 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c25800 0x400>;
|
||
|
|
interrupts = <3>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
||
|
|
resets = <&ccu RST_BUS_UART2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_otg: usb@1c13000 {
|
||
|
|
compatible = "allwinner,suniv-musb";
|
||
|
|
reg = <0x01c13000 0x0400>;
|
||
|
|
clocks = <&ccu CLK_BUS_OTG>;
|
||
|
|
resets = <&ccu RST_BUS_OTG>;
|
||
|
|
interrupts = <26>;
|
||
|
|
interrupt-names = "mc";
|
||
|
|
phys = <&usbphy 0>;
|
||
|
|
phy-names = "usb";
|
||
|
|
extcon = <&usbphy 0>;
|
||
|
|
allwinner,sram = <&otg_sram 1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usbphy: phy@1c13400 {
|
||
|
|
compatible = "allwinner,suniv-usb-phy";
|
||
|
|
reg = <0x01c13400 0x10>;
|
||
|
|
reg-names = "phy_ctrl";
|
||
|
|
clocks = <&ccu CLK_USB_PHY0>;
|
||
|
|
clock-names = "usb0_phy";
|
||
|
|
resets = <&ccu RST_USB_PHY0>;
|
||
|
|
reset-names = "usb0_reset";
|
||
|
|
#phy-cells = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
fe0: display-frontend@1e00000 {
|
||
|
|
compatible = "allwinner,suniv-display-frontend";
|
||
|
|
reg = <0x01e00000 0x20000>;
|
||
|
|
interrupts = <30>;
|
||
|
|
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
|
||
|
|
<&ccu CLK_DRAM_DE_FE>;
|
||
|
|
clock-names = "ahb", "mod",
|
||
|
|
"ram";
|
||
|
|
resets = <&ccu RST_BUS_DE_FE>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
ports {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
fe0_out: port@1 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <1>;
|
||
|
|
|
||
|
|
fe0_out_be0: endpoint@0 {
|
||
|
|
reg = <0>;
|
||
|
|
remote-endpoint = <&be0_in_fe0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
be0: display-backend@1e60000 {
|
||
|
|
compatible = "allwinner,suniv-display-backend";
|
||
|
|
reg = <0x01e60000 0x10000>;
|
||
|
|
reg-names = "be";
|
||
|
|
interrupts = <31>;
|
||
|
|
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
|
||
|
|
<&ccu CLK_DRAM_DE_BE>;
|
||
|
|
clock-names = "ahb", "mod",
|
||
|
|
"ram";
|
||
|
|
resets = <&ccu RST_BUS_DE_BE>;
|
||
|
|
reset-names = "be";
|
||
|
|
assigned-clocks = <&ccu CLK_DE_BE>;
|
||
|
|
assigned-clock-rates = <300000000>;
|
||
|
|
|
||
|
|
ports {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
be0_in: port@0 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0>;
|
||
|
|
|
||
|
|
be0_in_fe0: endpoint@0 {
|
||
|
|
reg = <0>;
|
||
|
|
remote-endpoint = <&fe0_out_be0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
be0_out: port@1 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <1>;
|
||
|
|
|
||
|
|
be0_out_tcon0: endpoint@0 {
|
||
|
|
reg = <0>;
|
||
|
|
remote-endpoint = <&tcon0_in_be0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|