144 lines
2.8 KiB
Plaintext
144 lines
2.8 KiB
Plaintext
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/*
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* Device Tree Source for the RZ/A1H RSK board
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*
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* Copyright (C) 2016 Renesas Electronics
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r7s72100.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
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/ {
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model = "RSKRZA1";
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compatible = "renesas,rskrza1", "renesas,r7s72100";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:115200n8";
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};
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memory@8000000 {
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device_type = "memory";
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reg = <0x08000000 0x02000000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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leds {
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status = "okay";
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compatible = "gpio-leds";
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led0 {
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gpios = <&port7 1 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&extal_clk {
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clock-frequency = <13330000>;
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};
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&usb_x1_clk {
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clock-frequency = <48000000>;
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};
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&rtc_x1_clk {
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clock-frequency = <32768>;
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};
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&pinctrl {
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/* Serial Console */
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scif2_pins: serial2 {
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pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
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<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
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};
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/* Ethernet */
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ether_pins: ether {
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/* Ethernet on Ports 1,2,3,5 */
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pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
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<RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
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<RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
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<RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
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<RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
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<RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
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<RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
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<RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
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<RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
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<RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
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<RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
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<RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
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<RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
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<RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
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<RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
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<RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
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<RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
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<RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
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};
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/* SDHI ch1 on CN1 */
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sdhi1_pins: sdhi1 {
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pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
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<RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
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<RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
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<RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
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<RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
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<RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
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<RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
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<RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
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};
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};
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&mtu2 {
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status = "okay";
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};
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ðer {
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pinctrl-names = "default";
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pinctrl-0 = <ðer_pins>;
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status = "okay";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&sdhi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi1_pins>;
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bus-width = <4>;
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status = "okay";
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};
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&ostm0 {
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status = "okay";
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};
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&ostm1 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&scif2 {
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pinctrl-names = "default";
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pinctrl-0 = <&scif2_pins>;
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status = "okay";
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};
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