717 lines
17 KiB
Plaintext
717 lines
17 KiB
Plaintext
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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memory {
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reg = <0x10000000 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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user {
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label = "debug";
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gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
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};
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};
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clocks {
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codec_osc: anaclk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_audio: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "cs42888_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb_h1_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg_vbus: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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sound-cs42888 {
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compatible = "fsl,imx6-sabreauto-cs42888",
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"fsl,imx-audio-cs42888";
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model = "imx-cs42888";
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audio-cpu = <&esai>;
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audio-asrc = <&asrc>;
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audio-codec = <&codec>;
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audio-routing =
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"Line Out Jack", "AOUT1L",
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"Line Out Jack", "AOUT1R",
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"Line Out Jack", "AOUT2L",
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"Line Out Jack", "AOUT2R",
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"Line Out Jack", "AOUT3L",
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"Line Out Jack", "AOUT3R",
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"Line Out Jack", "AOUT4L",
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"Line Out Jack", "AOUT4R",
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"AIN1L", "Line In Jack",
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"AIN1R", "Line In Jack",
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"AIN2L", "Line In Jack",
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"AIN2R", "Line In Jack";
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif",
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"fsl,imx-sabreauto-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif>;
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spdif-in;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm3 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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status = "okay";
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};
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i2cmux {
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compatible = "i2c-mux-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3mux>;
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mux-gpios = <&gpio5 4 0>;
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i2c-parent = <&i2c3>;
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idle-state = <0>;
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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adv7180: camera@21 {
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compatible = "adi,adv7180";
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reg = <0x21>;
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powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio1>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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port {
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adv7180_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <8>;
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};
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};
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};
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max7310_a: gpio@30 {
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compatible = "maxim,max7310";
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reg = <0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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max7310_b: gpio@32 {
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compatible = "maxim,max7310";
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reg = <0x32>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_max7310>;
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reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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max7310_c: gpio@34 {
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compatible = "maxim,max7310";
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reg = <0x34>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&ipu1_csi0_from_ipu1_csi0_mux {
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bus-width = <8>;
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};
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&ipu1_csi0_mux_from_parallel_sensor {
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remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
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bus-width = <8>;
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};
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&ipu1_csi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_csi0>;
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
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<&clks IMX6QDL_PLL4_BYPASS>,
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<&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
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<&clks IMX6QDL_PLL4_BYPASS_SRC>,
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
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};
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&ecspi1 {
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cs-gpios = <&gpio3 19 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
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status = "disabled"; /* pin conflict with WEIM NOR */
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32", "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&esai {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esai>;
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assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
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<&clks IMX6QDL_CLK_ESAI_EXTAL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
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<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
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fsl,err006687-workaround-present;
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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&hdmi {
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic: pfuze100@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3b_reg: sw3b {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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codec: cs42888@48 {
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compatible = "cirrus,cs42888";
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reg = <0x48>;
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clocks = <&codec_osc>;
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clock-names = "mclk";
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VA-supply = <®_audio>;
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VD-supply = <®_audio>;
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VLS-supply = <®_audio>;
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VLC-supply = <®_audio>;
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx6qdl-sabreauto {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
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MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
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MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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|
|
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||
|
|
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||
|
|
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi1_cs: ecspi1cs {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet: enetgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||
|
|
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||
|
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_esai: esaigrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
|
||
|
|
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
|
||
|
|
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
|
||
|
|
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
|
||
|
|
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
|
||
|
|
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||
|
|
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||
|
|
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||
|
|
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||
|
|
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||
|
|
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||
|
|
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3mux: i2c3muxgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ipu1_csi0: ipu1csi0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
|
||
|
|
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_max7310: max7310grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm3: pwm1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpt_input_capture0: gptinputcapture0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpt_input_capture1: gptinputcapture1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_spdif: spdifgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart4: uart4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||
|
|
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbotg: usbotggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3: usdhc3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
|
||
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_weim_cs0: weimcs0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_weim_nor: weimnorgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||
|
|
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||
|
|
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||
|
|
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&ldb {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
lvds-channel@0 {
|
||
|
|
fsl,data-mapping = "spwg";
|
||
|
|
fsl,data-width = <18>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
display-timings {
|
||
|
|
native-mode = <&timing0>;
|
||
|
|
timing0: hsd100pxn1 {
|
||
|
|
clock-frequency = <65000000>;
|
||
|
|
hactive = <1024>;
|
||
|
|
vactive = <768>;
|
||
|
|
hback-porch = <220>;
|
||
|
|
hfront-porch = <40>;
|
||
|
|
vback-porch = <21>;
|
||
|
|
vfront-porch = <7>;
|
||
|
|
hsync-len = <60>;
|
||
|
|
vsync-len = <10>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm3 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_pwm3>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&spdif {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_spdif>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart4 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_uart4>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usbh1 {
|
||
|
|
vbus-supply = <®_usb_h1_vbus>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usbotg {
|
||
|
|
vbus-supply = <®_usb_otg_vbus>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&usdhc3 {
|
||
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
||
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||
|
|
cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
|
||
|
|
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&weim {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
|
||
|
|
ranges = <0 0 0x08000000 0x08000000>;
|
||
|
|
status = "disabled"; /* pin conflict with SPI NOR */
|
||
|
|
|
||
|
|
nor@0,0 {
|
||
|
|
compatible = "cfi-flash";
|
||
|
|
reg = <0 0 0x02000000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
bank-width = <2>;
|
||
|
|
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
|
||
|
|
0x0000c000 0x1404a38e 0x00000000>;
|
||
|
|
};
|
||
|
|
};
|