278 lines
6.2 KiB
Plaintext
278 lines
6.2 KiB
Plaintext
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx1-pinfunc.h"
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#include <dt-bindings/clock/imx1-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* The decompressor and also some bootloaders rely on a
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* pre-existing /chosen node to be available to insert the
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* command line and merge other ATAGS info.
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* Also for U-Boot there must be a pre-existing /memory node.
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*/
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chosen {};
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memory { device_type = "memory"; reg = <0 0>; };
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &i2c;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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spi0 = &cspi1;
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spi1 = &cspi2;
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};
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aitc: aitc-interrupt-controller@223000 {
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compatible = "fsl,imx1-aitc", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x00223000 0x1000>;
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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compatible = "arm,arm920t";
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operating-points = <200000 1900000>;
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clock-latency = <62500>;
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clocks = <&clks IMX1_CLK_MCU>;
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voltage-tolerance = <5>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&aitc>;
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ranges;
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aipi@200000 {
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00200000 0x10000>;
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ranges;
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gpt1: timer@202000 {
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compatible = "fsl,imx1-gpt";
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reg = <0x00202000 0x1000>;
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interrupts = <59>;
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clocks = <&clks IMX1_CLK_HCLK>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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};
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gpt2: timer@203000 {
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compatible = "fsl,imx1-gpt";
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reg = <0x00203000 0x1000>;
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interrupts = <58>;
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clocks = <&clks IMX1_CLK_HCLK>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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};
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fb: fb@205000 {
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compatible = "fsl,imx1-fb";
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reg = <0x00205000 0x1000>;
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interrupts = <14>;
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clocks = <&clks IMX1_CLK_DUMMY>,
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<&clks IMX1_CLK_DUMMY>,
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<&clks IMX1_CLK_PER2>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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uart1: serial@206000 {
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compatible = "fsl,imx1-uart";
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reg = <0x00206000 0x1000>;
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interrupts = <30 29 26>;
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clocks = <&clks IMX1_CLK_HCLK>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@207000 {
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compatible = "fsl,imx1-uart";
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reg = <0x00207000 0x1000>;
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interrupts = <24 23 20>;
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clocks = <&clks IMX1_CLK_HCLK>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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pwm: pwm@208000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx1-pwm";
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reg = <0x00208000 0x1000>;
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interrupts = <34>;
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clocks = <&clks IMX1_CLK_DUMMY>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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};
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dma: dma@209000 {
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compatible = "fsl,imx1-dma";
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reg = <0x00209000 0x1000>;
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interrupts = <61 60>;
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clocks = <&clks IMX1_CLK_HCLK>,
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<&clks IMX1_CLK_DMA_GATE>;
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clock-names = "ipg", "ahb";
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#dma-cells = <1>;
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};
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uart3: serial@20a000 {
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compatible = "fsl,imx1-uart";
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reg = <0x0020a000 0x1000>;
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interrupts = <54 4 1>;
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clocks = <&clks IMX1_CLK_UART3_GATE>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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aipi@210000 {
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00210000 0x10000>;
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ranges;
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cspi1: cspi@213000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx1-cspi";
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reg = <0x00213000 0x1000>;
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interrupts = <41>;
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clocks = <&clks IMX1_CLK_DUMMY>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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i2c: i2c@217000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx1-i2c";
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reg = <0x00217000 0x1000>;
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interrupts = <39>;
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clocks = <&clks IMX1_CLK_HCLK>;
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status = "disabled";
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};
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cspi2: cspi@219000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx1-cspi";
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reg = <0x00219000 0x1000>;
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interrupts = <40>;
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clocks = <&clks IMX1_CLK_DUMMY>,
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<&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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clks: ccm@21b000 {
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compatible = "fsl,imx1-ccm";
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reg = <0x0021b000 0x1000>;
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#clock-cells = <1>;
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};
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iomuxc: iomuxc@21c000 {
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compatible = "fsl,imx1-iomuxc";
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reg = <0x0021c000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio1: gpio@21c000 {
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compatible = "fsl,imx1-gpio";
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reg = <0x0021c000 0x100>;
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interrupts = <11>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@21c100 {
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compatible = "fsl,imx1-gpio";
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reg = <0x0021c100 0x100>;
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interrupts = <12>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@21c200 {
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compatible = "fsl,imx1-gpio";
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reg = <0x0021c200 0x100>;
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interrupts = <13>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@21c300 {
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compatible = "fsl,imx1-gpio";
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reg = <0x0021c300 0x100>;
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interrupts = <62>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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weim: weim@220000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,imx1-weim";
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reg = <0x00220000 0x1000>;
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clocks = <&clks IMX1_CLK_DUMMY>;
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ranges = <
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0 0 0x10000000 0x02000000
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1 0 0x12000000 0x01000000
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2 0 0x13000000 0x01000000
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3 0 0x14000000 0x01000000
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4 0 0x15000000 0x01000000
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5 0 0x16000000 0x01000000
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>;
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status = "disabled";
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};
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esram: esram@300000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x20000>;
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};
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};
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};
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