325 lines
8.2 KiB
Plaintext
325 lines
8.2 KiB
Plaintext
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/*
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* SAMSUNG EXYNOS5260 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos5260-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "samsung,exynos5260", "samsung,exynos5";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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cci-control-port = <&cci_control1>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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cci-control-port = <&cci_control1>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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cci-control-port = <&cci_control0>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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cci-control-port = <&cci_control0>;
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};
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cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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cci-control-port = <&cci_control0>;
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};
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cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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cci-control-port = <&cci_control0>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock_top: clock-controller@10010000 {
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compatible = "samsung,exynos5260-clock-top";
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reg = <0x10010000 0x10000>;
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#clock-cells = <1>;
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};
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clock_peri: clock-controller@10200000 {
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compatible = "samsung,exynos5260-clock-peri";
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reg = <0x10200000 0x10000>;
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#clock-cells = <1>;
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};
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clock_egl: clock-controller@10600000 {
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compatible = "samsung,exynos5260-clock-egl";
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reg = <0x10600000 0x10000>;
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#clock-cells = <1>;
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};
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clock_kfc: clock-controller@10700000 {
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compatible = "samsung,exynos5260-clock-kfc";
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reg = <0x10700000 0x10000>;
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#clock-cells = <1>;
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};
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clock_g2d: clock-controller@10A00000 {
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compatible = "samsung,exynos5260-clock-g2d";
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reg = <0x10A00000 0x10000>;
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#clock-cells = <1>;
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};
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clock_mif: clock-controller@10CE0000 {
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compatible = "samsung,exynos5260-clock-mif";
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reg = <0x10CE0000 0x10000>;
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#clock-cells = <1>;
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};
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clock_mfc: clock-controller@11090000 {
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compatible = "samsung,exynos5260-clock-mfc";
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reg = <0x11090000 0x10000>;
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#clock-cells = <1>;
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};
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clock_g3d: clock-controller@11830000 {
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compatible = "samsung,exynos5260-clock-g3d";
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reg = <0x11830000 0x10000>;
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#clock-cells = <1>;
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};
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clock_fsys: clock-controller@122E0000 {
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compatible = "samsung,exynos5260-clock-fsys";
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reg = <0x122E0000 0x10000>;
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#clock-cells = <1>;
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};
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clock_aud: clock-controller@128C0000 {
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compatible = "samsung,exynos5260-clock-aud";
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reg = <0x128C0000 0x10000>;
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#clock-cells = <1>;
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};
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clock_isp: clock-controller@133C0000 {
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compatible = "samsung,exynos5260-clock-isp";
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reg = <0x133C0000 0x10000>;
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#clock-cells = <1>;
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};
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clock_gscl: clock-controller@13F00000 {
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compatible = "samsung,exynos5260-clock-gscl";
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reg = <0x13F00000 0x10000>;
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#clock-cells = <1>;
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};
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clock_disp: clock-controller@14550000 {
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compatible = "samsung,exynos5260-clock-disp";
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reg = <0x14550000 0x10000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10481000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-controller;
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reg = <0x10481000 0x1000>,
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<0x10482000 0x2000>,
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<0x10484000 0x2000>,
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<0x10486000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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chipid: chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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mct: mct@100B0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x100B0000 0x1000>;
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clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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};
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cci: cci@10F00000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10F00000 0x1000>;
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ranges = <0x0 0x10F00000 0x6000>;
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cci_control0: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control1: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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pinctrl_0: pinctrl@11600000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x11600000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_1: pinctrl@12290000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x12290000 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_2: pinctrl@128B0000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x128B0000 0x1000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu_system_controller: system-controller@10D50000 {
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compatible = "samsung,exynos5260-pmu", "syscon";
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reg = <0x10D50000 0x10000>;
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};
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uart0: serial@12C00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart1: serial@12C10000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C10000 0x100>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart2: serial@12C20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C20000 0x100>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart3: serial@12860000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12860000 0x100>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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mmc_0: mmc@12140000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12140000 0x2000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <64>;
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status = "disabled";
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};
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mmc_1: mmc@12150000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12150000 0x2000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <64>;
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status = "disabled";
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};
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mmc_2: mmc@12160000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12160000 0x2000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <64>;
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status = "disabled";
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};
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};
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};
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#include "exynos5260-pinctrl.dtsi"
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