69 lines
2.4 KiB
Plaintext
69 lines
2.4 KiB
Plaintext
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HiSilicon STB PCIe host bridge DT description
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The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
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It shares common functions with the DesignWare PCIe core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Additional properties are described here:
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Required properties
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- compatible: Should be one of the following strings:
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"hisilicon,hi3798cv200-pcie"
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- reg: Should contain sysctl, rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"control": control registers of PCIe controller;
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"rc-dbi": configuration space of PCIe controller;
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"config": configuration transaction space of PCIe controller.
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- bus-range: PCI bus numbers covered.
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- interrupts: MSI interrupt.
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- interrupt-names: Must include "msi" entries.
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- clocks: List of phandle and clock specifier pairs as listed in clock-names
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property.
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- clock-name: Must include the following entries:
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"aux": auxiliary gate clock;
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"pipe": pipe gate clock;
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"sys": sys gate clock;
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"bus": bus gate clock.
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- resets: List of phandle and reset specifier pairs as listed in reset-names
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property.
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- reset-names: Must include the following entries:
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"soft": soft reset;
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"sys": sys reset;
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"bus": bus reset.
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Optional properties:
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- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
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- phys: List of phandle and phy mode specifier, should be 0.
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- phy-names: Must be "phy".
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Example:
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pcie@f9860000 {
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compatible = "hisilicon,hi3798cv200-pcie";
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reg = <0xf9860000 0x1000>,
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<0xf0000000 0x2000>,
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<0xf2000000 0x01000000>;
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reg-names = "control", "rc-dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0 15>;
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num-lanes = <1>;
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ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
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0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg PCIE_AUX_CLK>,
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<&crg PCIE_PIPE_CLK>,
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<&crg PCIE_SYS_CLK>,
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<&crg PCIE_BUS_CLK>;
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clock-names = "aux", "pipe", "sys", "bus";
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resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
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reset-names = "soft", "sys", "bus";
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phys = <&combphy1 PHY_TYPE_PCIE>;
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phy-names = "phy";
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};
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