70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
|
GPIO-based multiplexer controller bindings
|
||
|
|
|
||
|
|
Define what GPIO pins are used to control a multiplexer. Or several
|
||
|
|
multiplexers, if the same pins control more than one multiplexer.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible : "gpio-mux"
|
||
|
|
- mux-gpios : list of gpios used to control the multiplexer, least
|
||
|
|
significant bit first.
|
||
|
|
- #mux-control-cells : <0>
|
||
|
|
* Standard mux-controller bindings as decribed in mux-controller.txt
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
- idle-state : if present, the state the mux will have when idle. The
|
||
|
|
special state MUX_IDLE_AS_IS is the default.
|
||
|
|
|
||
|
|
The multiplexer state is defined as the number represented by the
|
||
|
|
multiplexer GPIO pins, where the first pin is the least significant
|
||
|
|
bit. An active pin is a binary 1, an inactive pin is a binary 0.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
mux: mux-controller {
|
||
|
|
compatible = "gpio-mux";
|
||
|
|
#mux-control-cells = <0>;
|
||
|
|
|
||
|
|
mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&pioA 1 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
adc-mux {
|
||
|
|
compatible = "io-channel-mux";
|
||
|
|
io-channels = <&adc 0>;
|
||
|
|
io-channel-names = "parent";
|
||
|
|
|
||
|
|
mux-controls = <&mux>;
|
||
|
|
|
||
|
|
channels = "sync-1", "in", "out", "sync-2";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c-mux {
|
||
|
|
compatible = "i2c-mux";
|
||
|
|
i2c-parent = <&i2c1>;
|
||
|
|
|
||
|
|
mux-controls = <&mux>;
|
||
|
|
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
i2c@0 {
|
||
|
|
reg = <0>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
ssd1307: oled@3c {
|
||
|
|
/* ... */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c@3 {
|
||
|
|
reg = <3>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
pca9555: pca9555@20 {
|
||
|
|
/* ... */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|