226 lines
9.3 KiB
Plaintext
226 lines
9.3 KiB
Plaintext
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Device Tree Clock bindings for arch-sunxi
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
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"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
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"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
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"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
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"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
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"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
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"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-a10-axi-clk" - for the AXI clock
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"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
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"allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
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"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
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"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
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"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
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"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
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"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
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"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
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"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
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"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
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"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
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"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
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"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
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"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
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"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
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"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
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"allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
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"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
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"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
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"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
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"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
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"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
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"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
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"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
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"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
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"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
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"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
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"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
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"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
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"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
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"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
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"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
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"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
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"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
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"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
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"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
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"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
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"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
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"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
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"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
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"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
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"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
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"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
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"allwinner,sun6i-a31-display-clk" - for the display clocks
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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- clocks : shall be the input parent clock(s) phandle for the clock. For
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multiplexed clocks, the list order must match the hardware
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programming order.
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- #clock-cells : from common clock binding; shall be set to 0 except for
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the following compatibles where it shall be set to 1:
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"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
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"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
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"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
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"allwinner,*-mmc-config-clk"
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- clock-output-names : shall be the corresponding names of the outputs.
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If the clock module only has one output, the name shall be the
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module name.
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And "allwinner,*-usb-clk" clocks also require:
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- reset-cells : shall be set to 1
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The "allwinner,sun4i-a10-ve-clk" clock also requires:
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- reset-cells : shall be set to 0
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The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
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- #reset-cells : shall be set to 1
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- resets : shall be the reset control phandle for the mmc block.
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For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
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dummy clocks at 25 MHz and 125 MHz, respectively. See example.
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Clock consumers should specify the desired clocks they use with a
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"clocks" phandle cell. Consumers that are using a gated clock should
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provide an additional ID in their clock property. This ID is the
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offset of the bit controlling this particular gate in the register.
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For the other clocks with "#clock-cells" = 1, the additional ID shall
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refer to the index of the output.
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For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
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is the normal PLL6 output, or "pll6". The second output is rate doubled
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PLL6, or "pll6x2".
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The "allwinner,*-mmc-clk" clocks have three different outputs: the
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main clock, with the ID 0, and the output and sample clocks, with the
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IDs 1 and 2, respectively.
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The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
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per mmc controller. The number of outputs is determined by the size of
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the address block, which is related to the overall mmc block.
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For example:
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osc24M: clk@1c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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clock-output-names = "osc24M";
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};
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pll1: clk@1c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll5: clk@1c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: clk@1c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2";
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};
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cpu: cpu@1c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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clock-output-names = "cpu";
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};
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mmc0_clk: clk@1c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
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};
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mii_phy_tx_clk: clk@2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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gmac_int_tx_clk: clk@3 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac_int_tx";
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};
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gmac_clk: clk@1c20164 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x01c20164 0x4>;
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/*
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* The first clock must be fixed at 25MHz;
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* the second clock must be fixed at 125MHz
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*/
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clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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clock-output-names = "gmac";
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};
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mmc_config_clk: clk@1c13000 {
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compatible = "allwinner,sun9i-a80-mmc-config-clk";
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reg = <0x01c13000 0x10>;
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clocks = <&ahb0_gates 8>;
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clock-names = "ahb";
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resets = <&ahb0_resets 8>;
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reset-names = "ahb";
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#clock-cells = <1>;
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#reset-cells = <1>;
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clock-output-names = "mmc0_config", "mmc1_config",
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"mmc2_config", "mmc3_config";
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};
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