50 lines
1.9 KiB
Plaintext
50 lines
1.9 KiB
Plaintext
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* CoreSight CPU Debug Component:
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CoreSight CPU debug component are compliant with the ARMv8 architecture
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reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
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external debug module is mainly used for two modes: self-hosted debug and
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external debug, and it can be accessed from mmio region from Coresight
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and eventually the debug module connects with CPU for debugging. And the
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debug module provides sample-based profiling extension, which can be used
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to sample CPU program counter, secure state and exception level, etc;
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usually every CPU has one dedicated debug module to be connected.
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Required properties:
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- compatible : should be "arm,coresight-cpu-debug"; supplemented with
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"arm,primecell" since this driver is using the AMBA bus
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interface.
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- reg : physical base address and length of the register set.
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- clocks : the clock associated to this component.
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- clock-names : the name of the clock referenced by the code. Since we are
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using the AMBA framework, the name of the clock providing
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the interconnect should be "apb_pclk" and the clock is
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mandatory. The interface between the debug logic and the
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processor core is clocked by the internal CPU clock, so it
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is enabled with CPU clock by default.
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- cpu : the CPU phandle the debug module is affined to. When omitted
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the module is considered to belong to CPU0.
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Optional properties:
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- power-domains: a phandle to the debug power domain. We use "power-domains"
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binding to turn on the debug logic if it has own dedicated
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power domain and if necessary to use "cpuidle.off=1" or
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"nohlt" in the kernel command line or sysfs node to
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constrain idle states to ensure registers in the CPU power
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domain are accessible.
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Example:
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debug@f6590000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0 0xf6590000 0 0x1000>;
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clocks = <&sys_ctrl HI6220_DAPB_CLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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};
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