35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/* PR86731. Verify that the rs6000 gimple-folding code handles the
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left shift operation properly. This is a testcase variation that
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explicitly specifies -fwrapv, which is a condition for the
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gimple folding of the vec_sl() intrinsic. */
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/* specify -mpower8-vector, which provides vec_sl(long long,...) support. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-require-effective-target lp64 } */
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/* { dg-options "-maltivec -O3 -fwrapv -mpower8-vector " } */
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#include <altivec.h>
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vector unsigned long long splatu4(void)
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{
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vector unsigned long long mzero = {-1,-1};
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return (vector unsigned long long) vec_sl(mzero, mzero);
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}
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vector signed long long splats4(void)
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{
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vector unsigned long long mzero = {-1,-1};
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return (vector signed long long) vec_sl(mzero, mzero);
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}
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/* Codegen will consist of splat and shift instructions for most types.
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If folding is enabled, the vec_sl tests using vector long long type will
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generate a lvx instead of a vspltisw+vsld pair. */
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/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
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/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M} 2 } } */
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