ubuntu-buildroot/output/build/host-gcc-initial-11.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics
chenyf 8b0660016e 1 2024-04-01 23:19:46 +08:00
..
README 1 2024-04-01 23:19:46 +08:00
advsimd-intrinsics.exp 1 2024-04-01 23:19:46 +08:00
arm-neon-ref.h 1 2024-04-01 23:19:46 +08:00
bf16_dup.c 1 2024-04-01 23:19:46 +08:00
bf16_get-be.c 1 2024-04-01 23:19:46 +08:00
bf16_get.c 1 2024-04-01 23:19:46 +08:00
bf16_reinterpret.c 1 2024-04-01 23:19:46 +08:00
bf16_vect_copy_lane_1.c 1 2024-04-01 23:19:46 +08:00
bf16_vldN_lane_1.c 1 2024-04-01 23:19:46 +08:00
bf16_vldN_lane_2.c 1 2024-04-01 23:19:46 +08:00
bf16_vldn.c 1 2024-04-01 23:19:46 +08:00
bf16_vstN_lane_1.c 1 2024-04-01 23:19:46 +08:00
bf16_vstN_lane_2.c 1 2024-04-01 23:19:46 +08:00
bf16_vstn.c 1 2024-04-01 23:19:46 +08:00
bfcvt-compile.c 1 2024-04-01 23:19:46 +08:00
bfcvt-nobf16.c 1 2024-04-01 23:19:46 +08:00
bfcvt-nosimd.c 1 2024-04-01 23:19:46 +08:00
bfcvtn-nobf16.c 1 2024-04-01 23:19:46 +08:00
bfcvtnq2-untied.c 1 2024-04-01 23:19:46 +08:00
bfdot-1.c 1 2024-04-01 23:19:46 +08:00
bfdot-2.c 1 2024-04-01 23:19:46 +08:00
bfdot-3.c 1 2024-04-01 23:19:46 +08:00
bfmlalbt-compile.c 1 2024-04-01 23:19:46 +08:00
bfmmla-compile.c 1 2024-04-01 23:19:46 +08:00
binary_op.inc 1 2024-04-01 23:19:46 +08:00
binary_op_float.inc 1 2024-04-01 23:19:46 +08:00
binary_op_no64.inc 1 2024-04-01 23:19:46 +08:00
binary_sat_op.inc 1 2024-04-01 23:19:46 +08:00
binary_scalar_op.inc 1 2024-04-01 23:19:46 +08:00
cmp_fp_op.inc 1 2024-04-01 23:19:46 +08:00
cmp_op.inc 1 2024-04-01 23:19:46 +08:00
cmp_zero_op.inc 1 2024-04-01 23:19:46 +08:00
compute-ref-data.h 1 2024-04-01 23:19:46 +08:00
p64_p128.c 1 2024-04-01 23:19:46 +08:00
pr98852.c 1 2024-04-01 23:19:46 +08:00
smlal-smlsl-mull-optimized.c 1 2024-04-01 23:19:46 +08:00
ternary_scalar_op.inc 1 2024-04-01 23:19:46 +08:00
unary_op.inc 1 2024-04-01 23:19:46 +08:00
unary_sat_op.inc 1 2024-04-01 23:19:46 +08:00
unary_scalar_op.inc 1 2024-04-01 23:19:46 +08:00
vXXXhn.inc 1 2024-04-01 23:19:46 +08:00
vXXXhn_high.inc 1 2024-04-01 23:19:46 +08:00
vXXXl.inc 1 2024-04-01 23:19:46 +08:00
vXXXw.inc 1 2024-04-01 23:19:46 +08:00
vaba.c 1 2024-04-01 23:19:46 +08:00
vabal.c 1 2024-04-01 23:19:46 +08:00
vabd.c 1 2024-04-01 23:19:46 +08:00
vabdh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vabdl.c 1 2024-04-01 23:19:46 +08:00
vabs.c 1 2024-04-01 23:19:46 +08:00
vabsh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vadd.c 1 2024-04-01 23:19:46 +08:00
vaddh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vaddhn.c 1 2024-04-01 23:19:46 +08:00
vaddhn_high.c 1 2024-04-01 23:19:46 +08:00
vaddl.c 1 2024-04-01 23:19:46 +08:00
vaddw.c 1 2024-04-01 23:19:46 +08:00
vand.c 1 2024-04-01 23:19:46 +08:00
vbfmlalbt_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vbic.c 1 2024-04-01 23:19:46 +08:00
vbsl.c 1 2024-04-01 23:19:46 +08:00
vcage.c 1 2024-04-01 23:19:46 +08:00
vcageh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcagt.c 1 2024-04-01 23:19:46 +08:00
vcagth_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcale.c 1 2024-04-01 23:19:46 +08:00
vcaleh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcalt.c 1 2024-04-01 23:19:46 +08:00
vcalth_f16_1.c 1 2024-04-01 23:19:46 +08:00
vceq.c 1 2024-04-01 23:19:46 +08:00
vceqh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vceqz_1.c 1 2024-04-01 23:19:46 +08:00
vceqzh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcge.c 1 2024-04-01 23:19:46 +08:00
vcgeh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcgez_1.c 1 2024-04-01 23:19:46 +08:00
vcgezh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcgt.c 1 2024-04-01 23:19:46 +08:00
vcgth_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcgtz_1.c 1 2024-04-01 23:19:46 +08:00
vcgtzh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcle.c 1 2024-04-01 23:19:46 +08:00
vcleh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vclez_1.c 1 2024-04-01 23:19:46 +08:00
vclezh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcls.c 1 2024-04-01 23:19:46 +08:00
vclt.c 1 2024-04-01 23:19:46 +08:00
vclth_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcltz_1.c 1 2024-04-01 23:19:46 +08:00
vcltzh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vclz.c 1 2024-04-01 23:19:46 +08:00
vcnt.c 1 2024-04-01 23:19:46 +08:00
vcombine.c 1 2024-04-01 23:19:46 +08:00
vcopy_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vcopy_lane_bf16_indices_2.c 1 2024-04-01 23:19:46 +08:00
vcopy_laneq_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vcopy_laneq_bf16_indices_2.c 1 2024-04-01 23:19:46 +08:00
vcopyq_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vcopyq_lane_bf16_indices_2.c 1 2024-04-01 23:19:46 +08:00
vcopyq_laneq_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vcopyq_laneq_bf16_indices_2.c 1 2024-04-01 23:19:46 +08:00
vcreate.c 1 2024-04-01 23:19:46 +08:00
vcvt.c 1 2024-04-01 23:19:46 +08:00
vcvtX.inc 1 2024-04-01 23:19:46 +08:00
vcvt_f16.c 1 2024-04-01 23:19:46 +08:00
vcvt_fXX_fXX.c 1 2024-04-01 23:19:46 +08:00
vcvt_high_1.c 1 2024-04-01 23:19:46 +08:00
vcvta_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtah_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_s16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_s32_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_s64_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_u16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_u32_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_f16_u64_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_s16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_s32_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_s64_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_u16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_u32_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_f16_u64_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_n_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvth_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtm_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtmh_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtnh_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtp_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_s16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_s32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_s64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_u16_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_u32_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtph_u64_f16_1.c 1 2024-04-01 23:19:46 +08:00
vcvtx.c 1 2024-04-01 23:19:46 +08:00
vdiv_f16_1.c 1 2024-04-01 23:19:46 +08:00
vdivh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vdot-3-1.c 1 2024-04-01 23:19:46 +08:00
vdot-3-2.c 1 2024-04-01 23:19:46 +08:00
vdot-3-3.c 1 2024-04-01 23:19:46 +08:00
vdot-3-4.c 1 2024-04-01 23:19:46 +08:00
vdot-compile-2.c 1 2024-04-01 23:19:46 +08:00
vdot-compile.c 1 2024-04-01 23:19:46 +08:00
vdot-exec.c 1 2024-04-01 23:19:46 +08:00
vdup-vmov.c 1 2024-04-01 23:19:46 +08:00
vdup_lane.c 1 2024-04-01 23:19:46 +08:00
vduph_lane.c 1 2024-04-01 23:19:46 +08:00
vect-dot-qi.h 1 2024-04-01 23:19:46 +08:00
vect-dot-s8.c 1 2024-04-01 23:19:46 +08:00
vect-dot-u8.c 1 2024-04-01 23:19:46 +08:00
vector-complex.c 1 2024-04-01 23:19:46 +08:00
vector-complex_f16.c 1 2024-04-01 23:19:46 +08:00
veor.c 1 2024-04-01 23:19:46 +08:00
vext.c 1 2024-04-01 23:19:46 +08:00
vfma.c 1 2024-04-01 23:19:46 +08:00
vfma_n.c 1 2024-04-01 23:19:46 +08:00
vfmah_f16_1.c 1 2024-04-01 23:19:46 +08:00
vfmas_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vfmas_n_f16_1.c 1 2024-04-01 23:19:46 +08:00
vfmash_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vfms.c 1 2024-04-01 23:19:46 +08:00
vfms_vfma_n.c 1 2024-04-01 23:19:46 +08:00
vfmsh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vget_high.c 1 2024-04-01 23:19:46 +08:00
vget_lane.c 1 2024-04-01 23:19:46 +08:00
vget_low.c 1 2024-04-01 23:19:46 +08:00
vhadd.c 1 2024-04-01 23:19:46 +08:00
vhsub.c 1 2024-04-01 23:19:46 +08:00
vld1.c 1 2024-04-01 23:19:46 +08:00
vld1_dup.c 1 2024-04-01 23:19:46 +08:00
vld1_lane.c 1 2024-04-01 23:19:46 +08:00
vld1x2.c 1 2024-04-01 23:19:46 +08:00
vld1x3.c 1 2024-04-01 23:19:46 +08:00
vld1x4.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld2q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld3q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vld4q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vldX.c 1 2024-04-01 23:19:46 +08:00
vldX_dup.c 1 2024-04-01 23:19:46 +08:00
vldX_lane.c 1 2024-04-01 23:19:46 +08:00
vmax.c 1 2024-04-01 23:19:46 +08:00
vmaxh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmaxnm_1.c 1 2024-04-01 23:19:46 +08:00
vmaxnmh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmaxnmv_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmaxv_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmin.c 1 2024-04-01 23:19:46 +08:00
vminh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vminnm_1.c 1 2024-04-01 23:19:46 +08:00
vminnmh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vminnmv_f16_1.c 1 2024-04-01 23:19:46 +08:00
vminv_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmlX.inc 1 2024-04-01 23:19:46 +08:00
vmlX_lane.inc 1 2024-04-01 23:19:46 +08:00
vmlX_n.inc 1 2024-04-01 23:19:46 +08:00
vmlXl.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_high.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_high_lane.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_high_laneq.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_high_n.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_lane.inc 1 2024-04-01 23:19:46 +08:00
vmlXl_n.inc 1 2024-04-01 23:19:46 +08:00
vmla.c 1 2024-04-01 23:19:46 +08:00
vmla_lane.c 1 2024-04-01 23:19:46 +08:00
vmla_n.c 1 2024-04-01 23:19:46 +08:00
vmlal.c 1 2024-04-01 23:19:46 +08:00
vmlal_high.c 1 2024-04-01 23:19:46 +08:00
vmlal_high_lane.c 1 2024-04-01 23:19:46 +08:00
vmlal_high_laneq.c 1 2024-04-01 23:19:46 +08:00
vmlal_high_n.c 1 2024-04-01 23:19:46 +08:00
vmlal_lane.c 1 2024-04-01 23:19:46 +08:00
vmlal_n.c 1 2024-04-01 23:19:46 +08:00
vmls.c 1 2024-04-01 23:19:46 +08:00
vmls_lane.c 1 2024-04-01 23:19:46 +08:00
vmls_n.c 1 2024-04-01 23:19:46 +08:00
vmlsl.c 1 2024-04-01 23:19:46 +08:00
vmlsl_high.c 1 2024-04-01 23:19:46 +08:00
vmlsl_high_lane.c 1 2024-04-01 23:19:46 +08:00
vmlsl_high_laneq.c 1 2024-04-01 23:19:46 +08:00
vmlsl_high_n.c 1 2024-04-01 23:19:46 +08:00
vmlsl_lane.c 1 2024-04-01 23:19:46 +08:00
vmlsl_n.c 1 2024-04-01 23:19:46 +08:00
vmovl.c 1 2024-04-01 23:19:46 +08:00
vmovn.c 1 2024-04-01 23:19:46 +08:00
vmovn_high.c 1 2024-04-01 23:19:46 +08:00
vmul.c 1 2024-04-01 23:19:46 +08:00
vmul_lane.c 1 2024-04-01 23:19:46 +08:00
vmul_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmul_n.c 1 2024-04-01 23:19:46 +08:00
vmulh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulh_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmull.c 1 2024-04-01 23:19:46 +08:00
vmull_high.c 1 2024-04-01 23:19:46 +08:00
vmull_high_lane.c 1 2024-04-01 23:19:46 +08:00
vmull_high_laneq.c 1 2024-04-01 23:19:46 +08:00
vmull_high_n.c 1 2024-04-01 23:19:46 +08:00
vmull_lane.c 1 2024-04-01 23:19:46 +08:00
vmull_n.c 1 2024-04-01 23:19:46 +08:00
vmulx_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_laneq_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_laneq_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulx_n_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulxd_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxd_laneq_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulxh_lane_f16_1.c 1 2024-04-01 23:19:46 +08:00
vmulxq_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxq_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxq_laneq_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxq_laneq_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxs_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmulxs_laneq_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vmvn.c 1 2024-04-01 23:19:46 +08:00
vneg.c 1 2024-04-01 23:19:46 +08:00
vnegh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vorn.c 1 2024-04-01 23:19:46 +08:00
vorr.c 1 2024-04-01 23:19:46 +08:00
vpXXX.inc 1 2024-04-01 23:19:46 +08:00
vpXXXq.inc 1 2024-04-01 23:19:46 +08:00
vpadal.c 1 2024-04-01 23:19:46 +08:00
vpadd.c 1 2024-04-01 23:19:46 +08:00
vpaddl.c 1 2024-04-01 23:19:46 +08:00
vpaddq.c 1 2024-04-01 23:19:46 +08:00
vpmax.c 1 2024-04-01 23:19:46 +08:00
vpmin.c 1 2024-04-01 23:19:46 +08:00
vpminmaxnm_f16_1.c 1 2024-04-01 23:19:46 +08:00
vqabs.c 1 2024-04-01 23:19:46 +08:00
vqadd.c 1 2024-04-01 23:19:46 +08:00
vqdmlXl.inc 1 2024-04-01 23:19:46 +08:00
vqdmlXl_lane.inc 1 2024-04-01 23:19:46 +08:00
vqdmlXl_n.inc 1 2024-04-01 23:19:46 +08:00
vqdmlal.c 1 2024-04-01 23:19:46 +08:00
vqdmlal_lane.c 1 2024-04-01 23:19:46 +08:00
vqdmlal_n.c 1 2024-04-01 23:19:46 +08:00
vqdmlsl.c 1 2024-04-01 23:19:46 +08:00
vqdmlsl_lane.c 1 2024-04-01 23:19:46 +08:00
vqdmlsl_n.c 1 2024-04-01 23:19:46 +08:00
vqdmulh.c 1 2024-04-01 23:19:46 +08:00
vqdmulh_lane.c 1 2024-04-01 23:19:46 +08:00
vqdmulh_n.c 1 2024-04-01 23:19:46 +08:00
vqdmull.c 1 2024-04-01 23:19:46 +08:00
vqdmull_lane.c 1 2024-04-01 23:19:46 +08:00
vqdmull_n.c 1 2024-04-01 23:19:46 +08:00
vqmovn.c 1 2024-04-01 23:19:46 +08:00
vqmovn_high.c 1 2024-04-01 23:19:46 +08:00
vqmovun.c 1 2024-04-01 23:19:46 +08:00
vqmovun_high.c 1 2024-04-01 23:19:46 +08:00
vqneg.c 1 2024-04-01 23:19:46 +08:00
vqrdmlXh.inc 1 2024-04-01 23:19:46 +08:00
vqrdmlXh_lane.inc 1 2024-04-01 23:19:46 +08:00
vqrdmlah.c 1 2024-04-01 23:19:46 +08:00
vqrdmlah_lane.c 1 2024-04-01 23:19:46 +08:00
vqrdmlsh.c 1 2024-04-01 23:19:46 +08:00
vqrdmlsh_lane.c 1 2024-04-01 23:19:46 +08:00
vqrdmulh.c 1 2024-04-01 23:19:46 +08:00
vqrdmulh_lane.c 1 2024-04-01 23:19:46 +08:00
vqrdmulh_n.c 1 2024-04-01 23:19:46 +08:00
vqrshl.c 1 2024-04-01 23:19:46 +08:00
vqrshrn_high_n.c 1 2024-04-01 23:19:46 +08:00
vqrshrn_n.c 1 2024-04-01 23:19:46 +08:00
vqrshrun_high_n.c 1 2024-04-01 23:19:46 +08:00
vqrshrun_n.c 1 2024-04-01 23:19:46 +08:00
vqshl.c 1 2024-04-01 23:19:46 +08:00
vqshl_n.c 1 2024-04-01 23:19:46 +08:00
vqshlu_n.c 1 2024-04-01 23:19:46 +08:00
vqshrn_high_n.c 1 2024-04-01 23:19:46 +08:00
vqshrn_n.c 1 2024-04-01 23:19:46 +08:00
vqshrun_high_n.c 1 2024-04-01 23:19:46 +08:00
vqshrun_n.c 1 2024-04-01 23:19:46 +08:00
vqsub.c 1 2024-04-01 23:19:46 +08:00
vqtbX.c 1 2024-04-01 23:19:46 +08:00
vraddhn.c 1 2024-04-01 23:19:46 +08:00
vraddhn_high.c 1 2024-04-01 23:19:46 +08:00
vrecpe.c 1 2024-04-01 23:19:46 +08:00
vrecpeh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrecps.c 1 2024-04-01 23:19:46 +08:00
vrecpsh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrecpxh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vreinterpret.c 1 2024-04-01 23:19:46 +08:00
vreinterpret_p64.c 1 2024-04-01 23:19:46 +08:00
vreinterpret_p128.c 1 2024-04-01 23:19:46 +08:00
vrev.c 1 2024-04-01 23:19:46 +08:00
vrhadd.c 1 2024-04-01 23:19:46 +08:00
vrnd.c 1 2024-04-01 23:19:46 +08:00
vrndX.inc 1 2024-04-01 23:19:46 +08:00
vrnda.c 1 2024-04-01 23:19:46 +08:00
vrndah_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndi_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndih_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndm.c 1 2024-04-01 23:19:46 +08:00
vrndmh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndn.c 1 2024-04-01 23:19:46 +08:00
vrndnh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndp.c 1 2024-04-01 23:19:46 +08:00
vrndph_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrndx.c 1 2024-04-01 23:19:46 +08:00
vrndxh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrshl.c 1 2024-04-01 23:19:46 +08:00
vrshr_n.c 1 2024-04-01 23:19:46 +08:00
vrshrn_high_n.c 1 2024-04-01 23:19:46 +08:00
vrshrn_n.c 1 2024-04-01 23:19:46 +08:00
vrsqrte.c 1 2024-04-01 23:19:46 +08:00
vrsqrteh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrsqrts.c 1 2024-04-01 23:19:46 +08:00
vrsqrtsh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vrsra_n.c 1 2024-04-01 23:19:46 +08:00
vrsubhn.c 1 2024-04-01 23:19:46 +08:00
vrsubhn_high.c 1 2024-04-01 23:19:46 +08:00
vsXi_n.inc 1 2024-04-01 23:19:46 +08:00
vset_lane.c 1 2024-04-01 23:19:46 +08:00
vshl.c 1 2024-04-01 23:19:46 +08:00
vshl_n.c 1 2024-04-01 23:19:46 +08:00
vshll_n.c 1 2024-04-01 23:19:46 +08:00
vshr_n.c 1 2024-04-01 23:19:46 +08:00
vshrn_high_n.c 1 2024-04-01 23:19:46 +08:00
vshrn_n.c 1 2024-04-01 23:19:46 +08:00
vshuffle.inc 1 2024-04-01 23:19:46 +08:00
vsli_n.c 1 2024-04-01 23:19:46 +08:00
vsqrt_f16_1.c 1 2024-04-01 23:19:46 +08:00
vsqrth_f16_1.c 1 2024-04-01 23:19:46 +08:00
vsra_n.c 1 2024-04-01 23:19:46 +08:00
vsri_n.c 1 2024-04-01 23:19:46 +08:00
vst1_lane.c 1 2024-04-01 23:19:46 +08:00
vst1x2.c 1 2024-04-01 23:19:46 +08:00
vst1x3.c 1 2024-04-01 23:19:46 +08:00
vst1x4.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst2q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst3q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_bf16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_f16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_f32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_f64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_p8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_s8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_s16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_s32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_s64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_u8_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_u16_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_u32_indices_1.c 1 2024-04-01 23:19:46 +08:00
vst4q_lane_u64_indices_1.c 1 2024-04-01 23:19:46 +08:00
vstX_lane.c 1 2024-04-01 23:19:46 +08:00
vsub.c 1 2024-04-01 23:19:46 +08:00
vsubh_f16_1.c 1 2024-04-01 23:19:46 +08:00
vsubhn.c 1 2024-04-01 23:19:46 +08:00
vsubhn_high.c 1 2024-04-01 23:19:46 +08:00
vsubl.c 1 2024-04-01 23:19:46 +08:00
vsubw.c 1 2024-04-01 23:19:46 +08:00
vtbX.c 1 2024-04-01 23:19:46 +08:00
vtrn.c 1 2024-04-01 23:19:46 +08:00
vtrn_half.c 1 2024-04-01 23:19:46 +08:00
vtst.c 1 2024-04-01 23:19:46 +08:00
vuzp.c 1 2024-04-01 23:19:46 +08:00
vuzp_half.c 1 2024-04-01 23:19:46 +08:00
vzip.c 1 2024-04-01 23:19:46 +08:00
vzip_half.c 1 2024-04-01 23:19:46 +08:00

README

This directory contains executable tests for ARM/AArch64 Advanced SIMD
(Neon) intrinsics.

It is meant to cover execution cases of all the Advanced SIMD
intrinsics, but does not scan the generated assembler code.

The general framework is composed as follows:
- advsimd-intrinsics.exp: main dejagnu driver
- *.c: actual tests, generally one per intrinsinc family
- arm-neon-ref.h: contains macro definitions to save typing in actual
  test files
- compute-ref-data.h: contains input vectors definitions
- *.inc: generic tests, shared by several families of intrinsics. For
   instance, unary or binary operators

A typical .c test file starts with the following contents (look at
vld1.c and vaba.c for sample cases):
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"

Then, definitions of expected results, based on common input values,
as defined in compute-ref-data.h.
For example:
VECT_VAR_DECL(expected,int,16,4) [] = { 0x16, 0x17, 0x18, 0x19 };
defines the expected results of an operator generating int16x4 values.

The common input values defined in compute-ref-data.h have been chosen
to avoid corner-case values for most operators, yet exposing negative
values for signed operators. For this reason, their range is also
limited. For instance, the initialization of buffer_int16x4 will be
{ -16, -15, -14, -13 }.

The initialization of floating-point values is done via hex notation,
to avoid potential rounding problems.

To test special values and corner cases, specific initialization
values should be used in dedicated tests, to ensure proper coverage.
An example of this is vshl.

When a variant of an intrinsic is not available, its expected result
should be defined to the value of CLEAN_PATTERN_8 as defined in
arm-neon-ref.h. For example:
VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
if the given intrinsic has no variant producing an int64x1 result,
like the vcmp family (eg. vclt).

This is because the helper function (check_results(), defined in
arm-neon-ref.h), iterates over all the possible variants, to save
typing in each individual test file. Alternatively, one can directly
call the CHECK/CHECK_FP macros to check only a few expected results
(see vabs.c for an example).

Then, define the TEST_MSG string, which will be used when reporting errors.

Next, define the function performing the actual tests, in general
relying on the helpers provided by arm-neon-ref.h, which means:

* declare necessary vectors of suitable types: using
  DECL_VARIABLE_ALL_VARIANTS when all variants are supported, or the
  relevant of subset calls to DECL_VARIABLE.

* call clean_results() to initialize the 'results' buffers.

* initialize the input vectors, using VLOAD, VDUP or VSET_LANE (vld*
  tests do not need this step, since their actual purpose is to
  initialize vectors).

* execute the intrinsic on relevant variants, for instance using
  TEST_MACRO_ALL_VARIANTS_2_5.

* call check_results() to check that the results match the expected
  values.

A template test file could be:
=================================================================
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"

/* Expected results.  */
VECT_VAR_DECL(expected,int,8,8) [] = { 0xf6, 0xf7, 0xf8, 0xf9,
				       0xfa, 0xfb, 0xfc, 0xfd };
/* and as many others as necessary.  */

#define TEST_MSG "VMYINTRINSIC"
void exec_myintrinsic (void)
{
  /* my test: v4=vmyintrinsic(v1,v2,v3), then store the result.  */
#define TEST_VMYINTR(Q, T1, T2, W, N)					\
  VECT_VAR(vector_res, T1, W, N) =					\
    vmyintr##Q##_##T2##W(VECT_VAR(vector1, T1, W, N),			\
			 VECT_VAR(vector2, T1, W, N),			\
			 VECT_VAR(vector3, T1, W, N));			\
  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))

#define DECL_VMYINTR_VAR(VAR)			\
  DECL_VARIABLE(VAR, int, 8, 8);
/* And as many others as necessary.  */

  DECL_VMYINTR_VAR(vector1);
  DECL_VMYINTR_VAR(vector2);
  DECL_VMYINTR_VAR(vector3);
  DECL_VMYINTR_VAR(vector_res);

  clean_results ();

  /* Initialize input "vector1" from "buffer".  */
  VLOAD(vector1, buffer, , int, s, 8, 8);
/* And as many others as necessary.  */

  /* Choose init value arbitrarily.  */
  VDUP(vector2, , int, s, 8, 8, 1);
/* And as many others as necessary.  */

  /* Choose init value arbitrarily.  */
  VDUP(vector3, , int, s, 8, 8, -5);
/* And as many others as necessary.  */

  /* Execute the tests.  */
  TEST_VMYINTR(, int, s, 8, 8);
/* And as many others as necessary.  */

  check_results (TEST_MSG, "");
}

int main (void)
{
  exec_vmyintrinsic ();
  return 0;
}
=================================================================