602 lines
28 KiB
Modula-2
602 lines
28 KiB
Modula-2
/* Definitions of x86 tunable features.
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Copyright (C) 2013-2021 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Tuning for a given CPU XXXX consists of:
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- adding new CPU into:
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- adding PROCESSOR_XXX to processor_type (in i386.h)
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- possibly adding XXX into CPU attribute in i386.md
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- adding XXX to processor_alias_table (in i386.c)
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- introducing ix86_XXX_cost in i386.c
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- Stringop generation table can be build based on test_stringop
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- script (once rest of tuning is complete)
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- designing a scheduler model in
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- XXXX.md file
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- Updating ix86_issue_rate and ix86_adjust_cost in i386.md
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- possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
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and ix86_sched_init_global if those tricks are needed.
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- Tunning the flags bellow. Those are split into sections and each
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section is very roughly ordered by importance. */
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/*****************************************************************************/
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/* Scheduling flags. */
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/*****************************************************************************/
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/* X86_TUNE_SCHEDULE: Enable scheduling. */
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DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
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| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
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/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
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on modern chips. Preffer stores affecting whole integer register
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over partial stores. For example preffer MOVZBL or MOVQ to load 8bit
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value over movb. */
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DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
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m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
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| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
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| m_KNL | m_KNM | m_AMD_MULTIPLE | m_TREMONT
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| m_GENERIC)
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
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destinations to be 128bit to allow register renaming on 128bit SSE units,
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but usually results in one extra microop on 64bit SSE units.
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Experimental results shows that disabling this option on P4 brings over 20%
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SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
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that can be partly masked by careful scheduling of moves. */
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DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
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| m_BDVER | m_ZNVER | m_GENERIC)
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/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
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are resolved on SSE register parts instead of whole registers, so we may
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maintain just lower part of scalar values in proper format leaving the
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upper part undefined. */
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DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
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/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of flags
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set by instructions affecting just some flags (in particular shifts).
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This is because Core2 resolves dependencies on whole flags register
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and such sequences introduce false dependency on previous instruction
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setting full flags.
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The flags does not affect generation of INC and DEC that is controlled
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by X86_TUNE_USE_INCDEC. */
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DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
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m_CORE2)
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/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
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partial dependencies. */
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DEF_TUNE (X86_TUNE_MOVX, "movx",
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m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
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| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
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| m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE
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| m_CORE_AVX2 | m_TREMONT | m_GENERIC)
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/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
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full sized loads. */
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DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
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m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
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| m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
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| m_TREMONT | m_GENERIC)
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/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
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conditional jump instruction for 32 bit TARGET. */
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DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
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m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
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/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
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conditional jump instruction for TARGET_64BIT. */
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DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
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m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
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| m_ZNVER | m_GENERIC)
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/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
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subsequent conditional jump instruction when the condition jump
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check sign flag (SF) or overflow flag (OF). */
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DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
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m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
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| m_ZNVER | m_GENERIC)
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/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
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jump instruction when the alu instruction produces the CCFLAG consumed by
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the conditional jump instruction. */
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DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
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m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC)
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/*****************************************************************************/
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/* Function prologue, epilogue and function calling sequences. */
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/*****************************************************************************/
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/* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
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arguments in prologue/epilogue instead of separately for each call
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by push/pop instructions.
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This increase code size by about 5% in 32bit mode, less so in 64bit mode
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because parameters are passed in registers. It is considerable
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win for targets without stack engine that prevents multple push operations
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to happen in parallel. */
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DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
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considered on critical path. */
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DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
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m_PPRO | m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
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considered on critical path. */
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DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
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m_PPRO | m_ATHLON_K8)
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/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
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DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
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m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
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Some chips, like 486 and Pentium works faster with separate load
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and push instructions. */
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DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
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m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
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| m_GENERIC)
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/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
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over esp subtraction. */
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DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
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| m_LAKEMONT | m_K6_GEODE)
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/* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
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over esp subtraction. */
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DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMONT
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| m_K6_GEODE)
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/* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
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over esp addition. */
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DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT
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| m_LAKEMONT | m_PPRO)
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/* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
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over esp addition. */
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DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMONT)
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/*****************************************************************************/
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/* Branch predictor tuning */
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/*****************************************************************************/
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/* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
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instructions long. */
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DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
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/* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
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of conditional jump or directly preceded by other jump instruction.
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This is important for AND K8-AMDFAM10 because the branch prediction
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architecture expect at most one jump per 2 byte window. Failing to
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pad returns leads to misaligned return stack. */
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DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
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m_ATHLON_K8 | m_AMDFAM10)
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/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
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than 4 branch instructions in the 16 byte window. */
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DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
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| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL | m_ATHLON_K8
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| m_AMDFAM10)
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/*****************************************************************************/
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/* Integer instruction selection tuning */
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/*****************************************************************************/
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/* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
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at -O3. For the moment, the prefetching seems badly tuned for Intel
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chips. */
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DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
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m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
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/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
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on 16-bit immediate moves into memory on Core2 and Corei7. */
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DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
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/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
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as "add mem, reg". */
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DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
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/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
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Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
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Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop
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is output only when the values needs to be really merged, which is not
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done by GCC generated code. */
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DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
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~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
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| m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
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| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
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/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
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for DFmode copies */
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DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
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~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
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| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
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/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
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will impact LEA instruction selection. */
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DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
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| m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
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/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
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DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
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| m_KNL | m_KNM)
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/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
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vector path on AMD machines.
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FIXME: Do we need to enable this for core? */
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DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
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m_K8 | m_AMDFAM10)
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/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
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machines.
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FIXME: Do we need to enable this for core? */
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DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
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m_K8 | m_AMDFAM10)
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/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
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a conditional move. */
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DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
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| m_KNM | m_TREMONT | m_INTEL)
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/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
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as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
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DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
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/* X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB: Enable use of REP MOVSB/STOSB to
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move/set sequences of bytes with known size. */
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DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
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"prefer_known_rep_movsb_stosb",
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m_SKYLAKE | m_ALDERLAKE | m_CORE_AVX512)
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/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
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compact prologues and epilogues by issuing a misaligned moves. This
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requires target to handle misaligned moves and partial memory stalls
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reasonably well.
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FIXME: This may actualy be a win on more targets than listed here. */
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DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
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"misaligned_move_string_pro_epilogues",
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m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
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DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
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| m_BTVER | m_ZNVER | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
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| m_GENERIC)
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/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
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DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
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~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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| m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT))
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/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
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DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
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m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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| m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
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| m_TREMONT | m_GENERIC)
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/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
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for bit-manipulation instructions. */
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DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
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m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC)
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/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
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on hardware capabilities. Bdver3 hardware has a loop buffer which makes
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unrolling small loop less important. For, such architectures we adjust
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the unroll factor so that the unrolled loop fits the loop buffer. */
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DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
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/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
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if-converted sequence to one. */
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DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
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m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
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| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
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/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
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DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
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m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
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/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
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generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
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(signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */
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DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
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m_CORE_ALL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
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| m_GOLDMONT_PLUS | m_TREMONT )
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/*****************************************************************************/
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/* 387 instruction selection tuning */
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/*****************************************************************************/
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/* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
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integer operand.
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FIXME: Why this is disabled for modern chips? */
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DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
|
|
m_386 | m_486 | m_K6_GEODE)
|
|
|
|
/* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
|
|
integer operand. */
|
|
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
|
|
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
|
|
| m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
|
|
| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
|
|
|
|
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
|
|
DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
|
|
|
|
/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
|
|
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
|
|
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
|
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
|
|
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
|
|
|
|
/*****************************************************************************/
|
|
/* SSE instruction selection tuning */
|
|
/*****************************************************************************/
|
|
|
|
/* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
|
|
regs instead of memory. */
|
|
DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
|
|
m_CORE_ALL)
|
|
|
|
/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
|
|
of a sequence loading registers by parts. */
|
|
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
|
|
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
|
|
| m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
|
|
| m_TREMONT | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_GENERIC)
|
|
|
|
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
|
|
instead of a sequence loading registers by parts. */
|
|
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
|
|
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
|
|
| m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
|
|
| m_TREMONT | m_BDVER | m_ZNVER | m_GENERIC)
|
|
|
|
/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
|
|
precision 128bit instructions instead of double where possible. */
|
|
DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
|
|
m_BDVER | m_ZNVER)
|
|
|
|
/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
|
|
DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
|
|
m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
|
|
|
|
/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
|
|
xorps/xorpd and other variants. */
|
|
DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
|
|
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
|
|
| m_GENERIC)
|
|
|
|
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
|
|
to SSE registers. If disabled, the moves will be done by storing
|
|
the value to memory and reloading.
|
|
Enable this flag for generic - the only relevant architecture preferring
|
|
no inter-unit moves is Buldozer. While this makes small regression on SPECfp
|
|
scores (sub 0.3%), disabling inter-unit moves penalizes noticeably hand
|
|
written vectorized code which use i.e. _mm_set_epi16. */
|
|
DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
|
|
~(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER))
|
|
|
|
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
|
|
to integer registers. If disabled, the moves will be done by storing
|
|
the value to memory and reloading. */
|
|
DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
|
|
~m_ATHLON_K8)
|
|
|
|
/* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
|
|
to use both SSE and integer registers at a same time. */
|
|
DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
|
|
~(m_AMDFAM10 | m_BDVER))
|
|
|
|
/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
|
|
fp converts to destination register. */
|
|
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
|
|
m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
|
|
| m_TREMONT | m_INTEL)
|
|
|
|
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
|
|
from FP to FP. This form of instructions avoids partial write to the
|
|
destination. */
|
|
DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
|
|
m_AMDFAM10)
|
|
|
|
/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
|
|
from integer to FP. */
|
|
DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
|
|
|
|
/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
|
|
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
|
|
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
|
|
| m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
|
|
|
|
/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
|
|
DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
|
|
m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
|
|
|
|
/* X86_TUNE_USE_GATHER: Use gather instructions. */
|
|
DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",
|
|
~(m_ZNVER1 | m_ZNVER2 | m_GENERIC))
|
|
|
|
/* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
|
|
smaller FMA chain. */
|
|
DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER)
|
|
|
|
/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
|
|
smaller FMA chain. */
|
|
DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3)
|
|
|
|
/*****************************************************************************/
|
|
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
|
|
/*****************************************************************************/
|
|
|
|
/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
|
|
split. */
|
|
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
|
|
~(m_NEHALEM | m_SANDYBRIDGE))
|
|
|
|
/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
|
|
split. */
|
|
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
|
|
~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1))
|
|
|
|
/* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX256 ops are split into two AVX128 ops. */
|
|
DEF_TUNE (X86_TUNE_AVX256_SPLIT_REGS, "avx256_split_regs",m_BDVER | m_BTVER2
|
|
| m_ZNVER1)
|
|
|
|
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
|
|
the auto-vectorizer. */
|
|
DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2
|
|
| m_ZNVER1)
|
|
|
|
/* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
|
|
instructions in the auto-vectorizer. */
|
|
DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512)
|
|
|
|
/*****************************************************************************/
|
|
/* Historical relics: tuning flags that helps a specific old CPU designs */
|
|
/*****************************************************************************/
|
|
|
|
/* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
|
|
an integer register. */
|
|
DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
|
|
|
|
/* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
|
|
such as fsqrt, fprem, fsin, fcos, fsincos etc.
|
|
Should be enabled for all targets that always has coprocesor. */
|
|
DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
|
|
~(m_386 | m_486 | m_LAKEMONT))
|
|
|
|
/* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
|
|
inline strlen. This affects only -minline-all-stringops mode. By
|
|
default we always dispatch to a library since our internal strlen
|
|
is bad. */
|
|
DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
|
|
|
|
/* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
|
|
longer "sal $1, reg". */
|
|
DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
|
|
|
|
/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
|
|
of mozbl/movwl. */
|
|
DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
|
|
m_486 | m_PENT)
|
|
|
|
/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
|
|
and SImode multiply, but 386 and 486 do HImode multiply faster. */
|
|
DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
|
|
~(m_386 | m_486))
|
|
|
|
/* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
|
|
into 16bit/8bit when resulting sequence is shorter. For example
|
|
for "and $-65536, reg" to 16bit store of 0. */
|
|
DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix",
|
|
~(m_386 | m_486 | m_PENT | m_LAKEMONT))
|
|
|
|
/* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
|
|
such as "add $1, mem". */
|
|
DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write",
|
|
~(m_PENT | m_LAKEMONT))
|
|
|
|
/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
|
|
than a MOV. */
|
|
DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMONT)
|
|
|
|
/* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
|
|
but one byte longer. */
|
|
DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT)
|
|
|
|
/* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
|
|
use of partial registers by renaming. This improved performance of 16bit
|
|
code where upper halves of registers are not used. It also leads to
|
|
an penalty whenever a 16bit store is followed by 32bit use. This flag
|
|
disables production of such sequences in common cases.
|
|
See also X86_TUNE_HIMODE_MATH.
|
|
|
|
In current implementation the partial register stalls are not eliminated
|
|
very well - they can be introduced via subregs synthesized by combine
|
|
and can happen in caller/callee saving sequences. */
|
|
DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
|
|
|
|
/* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
|
|
corresponding 32bit arithmetic. */
|
|
DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
|
|
~m_PPRO)
|
|
|
|
/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid
|
|
partial register stalls on PentiumPro targets. */
|
|
DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
|
|
|
|
/* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
|
|
On PPro this flag is meant to avoid partial register stalls. */
|
|
DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
|
|
|
|
/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
|
|
directly to memory. */
|
|
DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
|
|
|
|
/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
|
|
DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
|
|
|
|
/* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
|
|
integer register. */
|
|
DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
|
|
|
|
/* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
|
|
operand that cannot be represented using a modRM byte. The XOR
|
|
replacement is long decoded, so this split helps here as well. */
|
|
DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
|
|
|
|
/* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
|
|
forms of instructions on K8 targets. */
|
|
DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
|
|
m_K8)
|
|
|
|
/*****************************************************************************/
|
|
/* This never worked well before. */
|
|
/*****************************************************************************/
|
|
|
|
/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
|
|
on simulation result. But after P4 was made, no performance benefit
|
|
was observed with branch hints. It also increases the code size.
|
|
As a result, icc never generates branch hints. */
|
|
DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", m_NONE)
|
|
|
|
/* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */
|
|
DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", m_ALL)
|
|
|
|
/* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
|
|
arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme
|
|
is usually used for RISC targets. */
|
|
DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", m_NONE)
|
|
|
|
/* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion
|
|
before a transfer of control flow out of the function. */
|
|
DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER, "emit_vzeroupper", ~m_KNL)
|