168 lines
5.0 KiB
C
168 lines
5.0 KiB
C
/* PLT fixups. Sparc 64-bit version.
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Copyright (C) 1997-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _DL_PLT_H
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#define _DL_PLT_H
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/* We have 4 cases to handle. And we code different code sequences
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for each one. I love V9 code models... */
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static inline void __attribute__ ((always_inline))
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sparc64_fixup_plt (struct link_map *map, const Elf64_Rela *reloc,
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Elf64_Addr *reloc_addr, Elf64_Addr value,
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Elf64_Addr high, int t)
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{
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unsigned int *insns = (unsigned int *) reloc_addr;
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Elf64_Addr plt_vaddr = (Elf64_Addr) reloc_addr;
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Elf64_Sxword disp = value - plt_vaddr;
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/* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap,
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in which case we'll be resolving all PLT entries and thus can
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optimize by overwriting instructions starting at the first PLT entry
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instruction and we need not be mindful of thread safety.
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Otherwise, 't' is '1'.
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Now move plt_vaddr up to the call instruction. */
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plt_vaddr += ((t + 1) * 4);
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/* PLT entries .PLT32768 and above look always the same. */
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if (__builtin_expect (high, 0) != 0)
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{
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*reloc_addr = value - map->l_addr;
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}
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/* Near destination. */
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else if (disp >= -0x800000 && disp < 0x800000)
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{
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unsigned int insn;
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/* ba,a */
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insn = 0x30800000 | ((disp >> 2) & 0x3fffff);
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if (disp >= -0x100000 && disp < 0x100000)
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{
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/* ba,a,pt %icc */
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insn = 0x30480000 | ((disp >> 2) & 0x07ffff);
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}
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/* As this is just one instruction, it is thread safe and so we
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can avoid the unnecessary sethi FOO, %g1. Each 64-bit PLT
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entry is 8 instructions long, so we can't run into the 'jmp'
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delay slot problems 32-bit PLTs can. */
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insns[0] = insn;
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__asm __volatile ("flush %0" : : "r" (insns));
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}
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/* 32-bit Sparc style, the target is in the lower 32-bits of
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address space. */
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else if (insns += t, (value >> 32) == 0)
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{
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/* sethi %hi(target), %g1
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jmpl %g1 + %lo(target), %g0 */
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insns[1] = 0x81c06000 | (value & 0x3ff);
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__asm __volatile ("flush %0 + 4" : : "r" (insns));
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insns[0] = 0x03000000 | ((unsigned int)(value >> 10));
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__asm __volatile ("flush %0" : : "r" (insns));
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}
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/* We can also get somewhat simple sequences if the distance between
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the target and the PLT entry is within +/- 2GB. */
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else if ((plt_vaddr > value
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&& ((plt_vaddr - value) >> 31) == 0)
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|| (value > plt_vaddr
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&& ((value - plt_vaddr) >> 31) == 0))
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{
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unsigned int displacement;
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if (plt_vaddr > value)
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displacement = (0 - (plt_vaddr - value));
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else
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displacement = value - plt_vaddr;
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/* mov %o7, %g1
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call displacement
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mov %g1, %o7 */
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insns[2] = 0x9e100001;
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__asm __volatile ("flush %0 + 8" : : "r" (insns));
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insns[1] = 0x40000000 | (displacement >> 2);
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__asm __volatile ("flush %0 + 4" : : "r" (insns));
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insns[0] = 0x8210000f;
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__asm __volatile ("flush %0" : : "r" (insns));
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}
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/* Worst case, ho hum... */
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else
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{
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unsigned int high32 = (value >> 32);
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unsigned int low32 = (unsigned int) value;
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/* ??? Some tricks can be stolen from the sparc64 egcs backend
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constant formation code I wrote. -DaveM */
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if (__glibc_unlikely (high32 & 0x3ff))
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{
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/* sethi %hh(value), %g1
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sethi %lm(value), %g5
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or %g1, %hm(value), %g1
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or %g5, %lo(value), %g5
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sllx %g1, 32, %g1
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jmpl %g1 + %g5, %g0
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nop */
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insns[5] = 0x81c04005;
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__asm __volatile ("flush %0 + 20" : : "r" (insns));
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insns[4] = 0x83287020;
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__asm __volatile ("flush %0 + 16" : : "r" (insns));
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insns[3] = 0x8a116000 | (low32 & 0x3ff);
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__asm __volatile ("flush %0 + 12" : : "r" (insns));
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insns[2] = 0x82106000 | (high32 & 0x3ff);
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}
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else
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{
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/* sethi %hh(value), %g1
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sethi %lm(value), %g5
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sllx %g1, 32, %g1
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or %g5, %lo(value), %g5
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jmpl %g1 + %g5, %g0
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nop */
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insns[4] = 0x81c04005;
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__asm __volatile ("flush %0 + 16" : : "r" (insns));
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insns[3] = 0x8a116000 | (low32 & 0x3ff);
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__asm __volatile ("flush %0 + 12" : : "r" (insns));
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insns[2] = 0x83287020;
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}
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__asm __volatile ("flush %0 + 8" : : "r" (insns));
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insns[1] = 0x0b000000 | (low32 >> 10);
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__asm __volatile ("flush %0 + 4" : : "r" (insns));
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insns[0] = 0x03000000 | (high32 >> 10);
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__asm __volatile ("flush %0" : : "r" (insns));
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}
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}
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#endif /* dl-plt.h */
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