From cbe33390a338428d74a4549cb28e25af42d7f7d9 Mon Sep 17 00:00:00 2001 From: "neeraj.dantu" Date: Sun, 21 Nov 2021 23:31:02 -0600 Subject: [PATCH 2/2] Add OSD32MP1-BRK build config Signed-off-by: Kory Maincent --- arch/arm/mach-stm32mp/Kconfig | 10 +- board/octavo/osd32mp1-brk/Kconfig | 13 + board/octavo/osd32mp1-brk/MAINTAINERS | 8 + board/octavo/osd32mp1-brk/Makefile | 9 + board/octavo/osd32mp1-brk/board.c | 631 +++++++++++++++++++++++++ configs/osd32mp1_brk_trusted_defconfig | 141 ++++++ 6 files changed, 811 insertions(+), 1 deletion(-) create mode 100644 board/octavo/osd32mp1-brk/Kconfig create mode 100644 board/octavo/osd32mp1-brk/MAINTAINERS create mode 100644 board/octavo/osd32mp1-brk/Makefile create mode 100644 board/octavo/osd32mp1-brk/board.c create mode 100644 configs/osd32mp1_brk_trusted_defconfig diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 44bfac9000..006855acad 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -92,6 +92,14 @@ config TARGET_DH_STM32MP1_PDK2 help Target the DH PDK2 development kit with STM32MP15x SoM. +config TARGET_OCTAVO_OSD32MP1_BRK + bool "Octavo OSD32MP1 BRK" + select STM32MP15x + imply BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT + help + Target the Octavo BRK board based on OSD32MP1 SiP. + endchoice config SYS_TEXT_BASE @@ -172,5 +180,5 @@ endif source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" source "board/st/stm32mp1/Kconfig" source "board/dhelectronics/dh_stm32mp1/Kconfig" - +source "board/octavo/osd32mp1-brk/Kconfig" endif diff --git a/board/octavo/osd32mp1-brk/Kconfig b/board/octavo/osd32mp1-brk/Kconfig new file mode 100644 index 0000000000..907a09c170 --- /dev/null +++ b/board/octavo/osd32mp1-brk/Kconfig @@ -0,0 +1,13 @@ +if TARGET_OCTAVO_OSD32MP1_BRK + +config SYS_BOARD + default "osd32mp1-brk" + +config SYS_VENDOR + default "octavo" + +config SYS_CONFIG_NAME + default "stm32mp1" + +source "board/st/common/Kconfig" +endif diff --git a/board/octavo/osd32mp1-brk/MAINTAINERS b/board/octavo/osd32mp1-brk/MAINTAINERS new file mode 100644 index 0000000000..9c0addbc21 --- /dev/null +++ b/board/octavo/osd32mp1-brk/MAINTAINERS @@ -0,0 +1,8 @@ +OCTAVO osd32mp1-brk BOARD +M: Martin Lesniak +M: Neeraj Dantu +S: Maintained +F: arch/arm/dts/stm32mp157c-osd32mp1-brk* +F: board/Octavo/osd32mp1-brk/ +F: configs/osd32mp1_brk_trusted_defconfig +F: include/configs/stm32mp1.h diff --git a/board/octavo/osd32mp1-brk/Makefile b/board/octavo/osd32mp1-brk/Makefile new file mode 100644 index 0000000000..b368b396a4 --- /dev/null +++ b/board/octavo/osd32mp1-brk/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += ../../st/common/stpmic1.o board.o + +obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o +obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o diff --git a/board/octavo/osd32mp1-brk/board.c b/board/octavo/osd32mp1-brk/board.c new file mode 100644 index 0000000000..fd97c9a390 --- /dev/null +++ b/board/octavo/osd32mp1-brk/board.c @@ -0,0 +1,631 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SYSCFG registers */ +#define SYSCFG_BOOTR 0x00 +#define SYSCFG_PMCSETR 0x04 +#define SYSCFG_IOCTRLSETR 0x18 +#define SYSCFG_ICNR 0x1C +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_PMCCLRR 0x44 + +#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 + +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) + +#define SYSCFG_CMPCR_SW_CTRL BIT(1) +#define SYSCFG_CMPCR_READY BIT(8) + +#define SYSCFG_CMPENSETR_MPU_EN BIT(0) + +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) + +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) + +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +int setup_mac_address(void) +{ + struct udevice *dev; + ofnode eeprom; + unsigned char enetaddr[6]; + int ret; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) /* ethaddr is already set */ + return 0; + + eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); + if (!ofnode_valid(eeprom)) { + printf("Invalid hardware path to EEPROM!\n"); + return -ENODEV; + } + + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + if (ret) { + printf("Cannot find EEPROM!\n"); + return ret; + } + + ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6); + if (ret) { + printf("Error reading configuration EEPROM!\n"); + return ret; + } + + if (is_valid_ethaddr(enetaddr)) + eth_env_set_enetaddr("ethaddr", enetaddr); + + return 0; +} + +int checkboard(void) +{ + char *mode; + const char *fdt_compat; + int fdt_compat_len; + + if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE)) + mode = "trusted - stm32image"; + else if (IS_ENABLED(CONFIG_TFABOOT)) + mode = "trusted"; + else + mode = "basic"; + + printf("Board: stm32mp1 in %s mode", mode); + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) + printf(" (%s)", fdt_compat); + puts("\n"); + + return 0; +} + +static void board_key_check(void) +{ + ofnode node; + struct gpio_desc gpio; + enum forced_boot_mode boot_mode = BOOT_NORMAL; + + if (!IS_ENABLED(CONFIG_FASTBOOT) && !IS_ENABLED(CONFIG_CMD_STM32PROG)) + return; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + if (IS_ENABLED(CONFIG_FASTBOOT)) { + if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,fastboot-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("Fastboot key pressed, "); + boot_mode = BOOT_FASTBOOT; + } + + dm_gpio_free(NULL, &gpio); + } + } + if (IS_ENABLED(CONFIG_CMD_STM32PROG)) { + if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,stm32prog-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("STM32Programmer key pressed, "); + boot_mode = BOOT_STM32PROG; + } + dm_gpio_free(NULL, &gpio); + } + } + if (boot_mode != BOOT_NORMAL) { + puts("entering download mode...\n"); + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_FORCED_MASK, + boot_mode); + } +} + +int g_dnl_board_usb_cable_connected(void) +{ + struct udevice *dwc2_udc_otg; + int ret; + + if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG)) + return -ENODEV; + ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC, + DM_GET_DRIVER(dwc2_udc_otg), + &dwc2_udc_otg); + if (!ret) + debug("dwc2_udc_otg init failed\n"); + + return dwc2_udc_B_session_valid(dwc2_udc_otg); +} + +#ifdef CONFIG_USB_GADGET_DOWNLOAD +#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 +#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (IS_ENABLED(CONFIG_DFU_OVER_USB) && + !strcmp(name, "usb_dnl_dfu")) + put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); + else if (IS_ENABLED(CONFIG_FASTBOOT) && + !strcmp(name, "usb_dnl_fastboot")) + put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, + &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} +#endif /* CONFIG_USB_GADGET_DOWNLOAD */ + +static int get_led(struct udevice **dev, char *led_string) +{ + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + if (!led_name) { + pr_debug("%s: could not find %s config string\n", + __func__, led_string); + return -ENOENT; + } + ret = led_get_by_label(led_name, dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int setup_led(enum led_state_t cmd) +{ + struct udevice *dev; + int ret; + + if (!CONFIG_IS_ENABLED(LED)) + return 0; + + ret = get_led(&dev, "u-boot,boot-led"); + if (ret) + return ret; + + ret = led_set_state(dev, cmd); + return ret; +} + +static void __maybe_unused led_error_blink(u32 nb_blink) +{ + int ret; + struct udevice *led; + u32 i; + + if (!nb_blink) + return; + + if (CONFIG_IS_ENABLED(LED)) { + ret = get_led(&led, "u-boot,error-led"); + if (!ret) { + /* make u-boot,error-led blinking */ + /* if U32_MAX and 125ms interval, for 17.02 years */ + for (i = 0; i < 2 * nb_blink; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + WATCHDOG_RESET(); + } + led_set_state(led, LEDST_ON); + } + } + + /* infinite: the boot process must be stopped */ + if (nb_blink == U32_MAX) + hang(); +} + +static void sysconf_init(void) +{ + u8 *syscfg; + struct udevice *pwr_dev; + struct udevice *pwr_reg; + struct udevice *dev; + u32 otp = 0; + int ret; + u32 bootr, val; + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + /* interconnect update : select master using the port 1 */ + /* LTDC = AXI_M9 */ + /* GPU = AXI_M8 */ + /* today information is hardcoded in U-Boot */ + writel(BIT(9), syscfg + SYSCFG_ICNR); + + /* disable Pull-Down for boot pin connected to VDD */ + bootr = readl(syscfg + SYSCFG_BOOTR); + bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); + bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; + writel(bootr, syscfg + SYSCFG_BOOTR); + + /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI + * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. + * The customer will have to disable this for low frequencies + * or if AFMUX is selected but the function not used, typically for + * TRACE. Otherwise, impact on power consumption. + * + * WARNING: + * enabling High Speed mode while VDD>2.7V + * with the OTP product_below_2v5 (OTP 18, BIT 13) + * erroneously set to 1 can damage the IC! + * => U-Boot set the register only if VDD < 2.7V (in DT) + * but this value need to be consistent with board design + */ + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(stm32mp_pwr_pmic), + &pwr_dev); + if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } + + ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); + if (ret > 0) + otp = otp & BIT(13); + + /* get VDD = vdd-supply */ + ret = device_get_supply_regulator(pwr_dev, "vdd-supply", + &pwr_reg); + + /* check if VDD is Low Voltage */ + if (!ret) { + if (regulator_get_value(pwr_reg) < 2700000) { + writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | + SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | + SYSCFG_IOCTRLSETR_HSLVEN_ETH | + SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | + SYSCFG_IOCTRLSETR_HSLVEN_SPI, + syscfg + SYSCFG_IOCTRLSETR); + + if (!otp) + pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); + } else { + if (otp) + pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); + } + } else { + debug("VDD unknown"); + } + } + + /* activate automatic I/O compensation + * warning: need to ensure CSI enabled and ready in clock driver + */ + writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); + + /* poll until ready (1s timeout) */ + ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val, + val & SYSCFG_CMPCR_READY, + 1000000); + if (ret) { + pr_err("SYSCFG: I/O compensation failed, timeout.\n"); + led_error_blink(10); + } + + clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); +} + +/* board dependent setup after realloc */ +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; + + if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) + gpio_hog_probe_all(); + + board_key_check(); + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) + regulators_enable_boot_on(_DEBUG); + + if (!IS_ENABLED(CONFIG_TFABOOT)) + sysconf_init(); + + if (CONFIG_IS_ENABLED(LED)) + led_default_state(); + + return 0; +} + +int board_late_init(void) +{ + char *boot_device; + const void *fdt_compat; + int fdt_compat_len; + int ret; + u32 otp; + struct udevice *dev; + char buf[10]; + char dtb_name[256]; + int buf_len; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) { + env_set("board_name", fdt_compat); + } else { + env_set("board_name", fdt_compat + 3); + + buf_len = sizeof(dtb_name); + strncpy(dtb_name, fdt_compat + 3, buf_len); + buf_len -= strlen(fdt_compat + 3); + strncat(dtb_name, ".dtb", buf_len); + env_set("fdtfile", dtb_name); + } + } + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + if (ret > 0 && otp) { + snprintf(buf, sizeof(buf), "0x%04x", otp >> 16); + env_set("board_id", buf); + + snprintf(buf, sizeof(buf), "0x%04x", + ((otp >> 8) & 0xF) - 1 + 0xA); + env_set("board_rev", buf); + } + } + + /* Check the boot-source to disable bootdelay */ + boot_device = env_get("boot_device"); + if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) + env_set("bootdelay", "0"); + + return 0; +} + +void board_quiesce_devices(void) +{ + setup_led(LEDST_OFF); +} + +/* eth init function : weak called in eqos driver */ +int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type, ulong rate) +{ + u8 *syscfg; + u32 value; + bool eth_clk_sel_reg = false; + bool eth_ref_clk_sel_reg = false; + + /* Gigabit Ethernet 125MHz clock selection. */ + eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + + /* Ethernet 50Mhz RMII clock selection */ + eth_ref_clk_sel_reg = + dev_read_bool(dev, "st,eth_ref_clk_sel"); + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + if (!syscfg) + return -ENODEV; + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); + break; + case PHY_INTERFACE_MODE_GMII: + if (eth_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | + SYSCFG_PMCSETR_ETH_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); + break; + case PHY_INTERFACE_MODE_RMII: + if (eth_ref_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_RMII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_RMII; + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + if (eth_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_RGMII | + SYSCFG_PMCSETR_ETH_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_RGMII; + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); + break; + default: + debug("%s: Do not manage %d interface\n", + __func__, interface_type); + /* Do not manage others interfaces */ + return -EINVAL; + } + + /* clear and set ETH configuration bits */ + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, + syscfg + SYSCFG_PMCCLRR); + writel(value, syscfg + SYSCFG_PMCSETR); + + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 bootmode = get_bootmode(); + + if (prio) + return ENVL_UNKNOWN; + + switch (bootmode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) + return ENVL_EXT4; + else + return ENVL_NOWHERE; + + case BOOT_FLASH_NAND: + case BOOT_FLASH_SPINAND: + if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI)) + return ENVL_UBI; + else + return ENVL_NOWHERE; + + case BOOT_FLASH_NOR: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + else + return ENVL_NOWHERE; + + default: + return ENVL_NOWHERE; + } +} + +const char *env_ext4_get_intf(void) +{ + u32 bootmode = get_bootmode(); + + switch (bootmode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + return "mmc"; + default: + return ""; + } +} + +const char *env_ext4_get_dev_part(void) +{ + static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"}; + u32 bootmode = get_bootmode(); + + return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1]; +} + +int mmc_get_env_dev(void) +{ + u32 bootmode; + + if (CONFIG_SYS_MMC_ENV_DEV >= 0) + return CONFIG_SYS_MMC_ENV_DEV; + + bootmode = get_bootmode(); + + /* use boot instance to select the correct mmc device identifier */ + return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +static void board_copro_image_process(ulong fw_image, size_t fw_size) +{ + int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ + + if (!rproc_is_initialized()) + if (rproc_init()) { + printf("Remote Processor %d initialization failed\n", + id); + return; + } + + ret = rproc_load(id, fw_image, fw_size); + printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", + id, fw_image, fw_size, ret ? " Failed!" : " Success!"); + + if (!ret) + rproc_start(id); +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); diff --git a/configs/osd32mp1_brk_trusted_defconfig b/configs/osd32mp1_brk_trusted_defconfig new file mode 100644 index 0000000000..6d41af8886 --- /dev/null +++ b/configs/osd32mp1_brk_trusted_defconfig @@ -0,0 +1,141 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_ENV_OFFSET=0x480000 +CONFIG_ENV_SECT_SIZE=0x40000 +# CONFIG_TARGET_ST_STM32MP15x=y +CONFIG_TARGET_OCTAVO_OSD32MP1_BRK=y +CONFIG_CMD_STM32PROG=y +CONFIG_ENV_OFFSET_REDUND=0x4C0000 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-osd32mp1-brk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_PROMPT="OSD32MP> " +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="UBI" +CONFIG_ENV_UBI_VOLUME="uboot_config" +CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_STM32_ADC=y +CONFIG_CLK_SCMI=y +CONFIG_SET_DFU_ALT_INFO=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x02000000 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_GPIO_HOG=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_STM32_FMC2_EBI=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PHY_STM32_USBPHYC=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_STM32_VREFBUF=y +CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_RESET_SCMI=y +CONFIG_DM_RNG=y +CONFIG_RNG_STM32MP1=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_SPI=y +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0483 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_DSI=y +CONFIG_VIDEO_STM32_MAX_XRES=1280 +CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_ERRNO_STR=y +CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_LMB_RESERVED_REGIONS=16 -- 2.25.1