135 lines
3.5 KiB
ArmAsm
135 lines
3.5 KiB
ArmAsm
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/* Copyright (C) 2006-2021 Free Software Foundation, Inc.
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Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
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on behalf of Synopsys Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "arc-ieee-754.h"
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#if 0 /* DEBUG */
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FUNC(__truncdfsf2)
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.global __truncdfsf2
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.balign 4
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__truncdfsf2:
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push_s blink
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push_s r0
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bl.d __truncdfsf2_c
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push_s r1
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mov_s r2,r0
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pop_s r1
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ld r0,[sp]
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bl.d __truncdfsf2_asm
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st r2,[sp]
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pop_s r1
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pop_s blink
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cmp r0,r1
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jeq_s [blink]
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and r12,r0,r1
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bic.f 0,0x7f800000,r12
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bne 0f
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bmsk.f 0,r0,22
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bmsk.ne.f r1,r1,22
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jne_s [blink] ; both NaN -> OK
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0: bl abort
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ENDFUNC(__truncdfsf2)
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#define __truncdfsf2 __truncdfsf2_asm
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#endif /* DEBUG */
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.global __truncdfsf2
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.balign 4
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FUNC(__truncdfsf2)
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__truncdfsf2:
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lsr r2,DBL0H,20
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asl_s DBL0H,DBL0H,12
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sub r12,r2,0x380
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bclr.f r3,r12,11
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brhs r3,0xff,.Lill_exp
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beq_l .Ldenorm0
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asl_s r12,r12,23
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tst DBL0L, \
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0x2fffffff /* Check if msb guard bit wants rounding up. */
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lsr_s DBL0L,DBL0L,28
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lsr_s DBL0H,DBL0H,8
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add.ne DBL0L,DBL0L,1
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add_s DBL0H,DBL0H,DBL0L
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lsr_s DBL0H,DBL0H
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btst_s r2,11
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add_s r0,DBL0H,r12
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j_s.d [blink]
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bxor.ne r0,r0,31
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.balign 4
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.Lill_exp:
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bbit1 r2,10,.Linf_nan
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bmsk_s r12,r12,9
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rsub.f r12,r12,8+0x400-32 ; Go from 9 to 1 guard bit in MSW. */
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bhs_s .Lzero
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lsr r3,DBL0L,21
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rrc DBL0H,DBL0H ; insert leading 1
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asl.f 0,DBL0L,8 ; check lower 24 guard bits
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add_s r3,DBL0H,r3
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add.pnz r3,r3,1 ; assemble fraction with compressed guard bits.
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lsr r0,r3,r12
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neg_s r12,r12
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btst_s r0,1
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asl.eq.f r3,r3,r12
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add.ne r0,r0,1
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btst_s r2,11
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lsr_s r0,r0
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j_s.d [blink]
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bxor.ne r0,r0,31
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.Lzero:
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lsr_s r2,r2,11
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j_s.d [blink]
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asl r0,r2,31
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.Ldenorm0:
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asl_s r12,r12,20
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tst DBL0L, \
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0x5fffffff /* Check if msb guard bit wants rounding up. */
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lsr_s DBL0L,DBL0L,29
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lsr_s DBL0H,DBL0H,9
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add.ne DBL0L,DBL0L,1
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bset_s DBL0H,DBL0H,23
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add_s DBL0H,DBL0H,DBL0L
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lsr_s DBL0H,DBL0H
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j_s.d [blink]
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add_l r0,DBL0H,r12
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/* We would generally say that NaNs must have a non-zero high fraction part,
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but to allow hardware double precision floating point to interoperate
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with single precision software floating point, we make an exception here.
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The cost is to replace a tst_s DBL0H with an or.f DBL0L,DBL0L,DBL0H .
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As we start out unaligned, and there is an odd number of other short insns,
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we have a choice of letting this cost us a misalign penalty or
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4 more bytes (if we align the code). We choose the former here because
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infinity / NaN is not expected to be prevalent in time-critical code. */
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.Linf_nan:
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or.f DBL0L,DBL0L,DBL0H
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mov_s r0,1
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add.ne r2,r2,1
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tst r2,0x7ff
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asl.ne r0,r0,23
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btst_s r12,11
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neg r0,r0
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j_s.d [blink]
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bxor.eq r0,r0,31
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ENDFUNC(__truncdfsf2)
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