104 lines
2.1 KiB
C
104 lines
2.1 KiB
C
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/* Definitions for option handling of Andes NDS32 cpu for GNU compiler
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Copyright (C) 2012-2021 Free Software Foundation, Inc.
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Contributed by Andes Technology Corporation.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef NDS32_OPTS_H
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#define NDS32_OPTS_H
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#define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
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#define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
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/* The various ANDES ISA. */
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enum nds32_arch_type
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{
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ARCH_V2,
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ARCH_V3,
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ARCH_V3J,
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ARCH_V3M,
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ARCH_V3F,
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ARCH_V3S
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};
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/* The various ANDES CPU. */
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enum nds32_cpu_type
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{
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CPU_N6,
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CPU_N7,
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CPU_N8,
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CPU_E8,
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CPU_N9,
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CPU_N10,
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CPU_GRAYWOLF,
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CPU_N12,
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CPU_N13,
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CPU_SIMPLE
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};
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/* The code model defines the address generation strategy. */
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enum nds32_cmodel_type
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{
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CMODEL_SMALL,
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CMODEL_MEDIUM,
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CMODEL_LARGE
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};
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/* The code model defines the address generation strategy. */
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enum nds32_ict_model_type
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{
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ICT_MODEL_SMALL,
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ICT_MODEL_LARGE
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};
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/* Multiply instruction configuration. */
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enum nds32_mul_type
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{
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MUL_TYPE_FAST_1,
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MUL_TYPE_FAST_2,
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MUL_TYPE_SLOW
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};
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/* Register ports configuration. */
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enum nds32_register_ports
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{
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REG_PORT_3R2W,
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REG_PORT_2R1W
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};
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/* Which ABI to use. */
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enum abi_type
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{
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NDS32_ABI_V2,
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NDS32_ABI_V2_FP_PLUS
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};
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/* The various FPU number of registers. */
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enum float_reg_number
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{
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NDS32_CONFIG_FPU_0,
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NDS32_CONFIG_FPU_1,
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NDS32_CONFIG_FPU_2,
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NDS32_CONFIG_FPU_3,
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NDS32_CONFIG_FPU_4,
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NDS32_CONFIG_FPU_5,
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NDS32_CONFIG_FPU_6,
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NDS32_CONFIG_FPU_7
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};
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#endif
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