352 lines
10 KiB
Markdown
352 lines
10 KiB
Markdown
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;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; bit shifting
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; Shifts are unusual for m32c. We only support shifting in one
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; "direction" but the shift count is signed. Also, immediate shift
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; counts have a limited range, and variable shift counts have to be in
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; $r1h which GCC normally doesn't even know about.
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; Other than compensating for the above, the patterns below are pretty
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; straightforward.
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(define_insn "ashlqi3_i"
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[(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
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(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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sha.b\t%2,%0
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mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "ashrqi3_i"
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[(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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sha.b\t%2,%0
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mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "lshrqi3_i"
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[(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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shl.b\t%2,%0
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mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
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[(set_attr "flags" "szc,szc")]
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)
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(define_expand "ashlqi3"
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[(parallel [(set (match_operand:QI 0 "mra_operand" "")
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(ashift:QI (match_operand:QI 1 "mra_operand" "")
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(match_operand:QI 2 "general_operand" "")))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, 1, ASHIFT))
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DONE;"
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)
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(define_expand "ashrqi3"
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[(parallel [(set (match_operand:QI 0 "mra_operand" "")
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(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "general_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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DONE;"
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)
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(define_expand "lshrqi3"
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[(parallel [(set (match_operand:QI 0 "mra_operand" "")
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(lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "general_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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DONE;"
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)
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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(define_insn "ashlhi3_i"
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[(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
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(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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sha.w\t%2,%0
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mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "ashrhi3_i"
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[(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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sha.w\t%2,%0
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mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "lshrhi3_i"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
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(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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""
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"@
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shl.w\t%2,%0
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mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
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[(set_attr "flags" "szc,szc")]
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)
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(define_expand "ashlhi3"
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[(parallel [(set (match_operand:HI 0 "mra_operand" "")
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(ashift:HI (match_operand:HI 1 "mra_operand" "")
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(match_operand:QI 2 "general_operand" "")))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, 1, ASHIFT))
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DONE;"
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)
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(define_expand "ashrhi3"
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[(parallel [(set (match_operand:HI 0 "mra_operand" "")
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(ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "general_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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DONE;"
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)
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(define_expand "lshrhi3"
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[(parallel [(set (match_operand:HI 0 "mra_operand" "")
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(lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "general_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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""
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"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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DONE;"
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)
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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(define_insn "ashlpsi3_i"
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[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "ashrpsi3_i"
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[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "lshrpsi3_i"
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[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
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(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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"@
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shl.l\t%2,%0
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mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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[(set_attr "flags" "szc,szc")]
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)
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(define_expand "ashlpsi3"
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[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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(ashift:PSI (match_operand:PSI 1 "mra_operand" "")
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(match_operand:QI 2 "shiftcount_operand" "")))
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(clobber (match_scratch:HI 3 ""))])]
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"TARGET_A24"
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"if (m32c_prepare_shift (operands, 1, ASHIFT))
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DONE;"
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)
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(define_expand "ashrpsi3"
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[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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"TARGET_A24"
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"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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DONE;"
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)
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(define_expand "lshrpsi3"
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[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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(clobber (match_scratch:HI 3 ""))])]
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"TARGET_A24"
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"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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DONE;"
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)
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; The m16c has a maximum shift count of -16..16, even when in a
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; register. It's optimal to use multiple shifts of -8..8 rather than
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; loading larger constants into R1H multiple time. The m32c can shift
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; -32..32 either via immediates or in registers. Hence, separate
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; patterns.
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(define_insn "ashlsi3_16"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A16"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "ashrsi3_16"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A16"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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[(set_attr "flags" "oszc,oszc")]
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)
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(define_insn "lshrsi3_16"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A16"
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"@
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shl.l\t%2,%0
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mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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[(set_attr "flags" "szc,szc")]
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)
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(define_insn "ashlsi3_24"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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)
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(define_insn "ashrsi3_24"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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"@
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sha.l\t%2,%0
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mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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)
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(define_insn "lshrsi3_24"
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[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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(clobber (match_scratch:HI 3 "=X,R1w"))]
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"TARGET_A24"
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||
|
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"@
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shl.l\t%2,%0
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mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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)
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|
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(define_expand "ashlsi3"
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||
|
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[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
|
||
|
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(ashift:SI (match_operand:SI 1 "r0123_operand" "")
|
||
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(match_operand:QI 2 "mrai_operand" "")))
|
||
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(clobber (match_scratch:HI 3 ""))])]
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||
|
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""
|
||
|
|
"if (m32c_prepare_shift (operands, 1, ASHIFT))
|
||
|
|
DONE;"
|
||
|
|
)
|
||
|
|
|
||
|
|
(define_expand "ashrsi3"
|
||
|
|
[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
|
||
|
|
(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
|
||
|
|
(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
|
||
|
|
(clobber (match_scratch:HI 3 ""))])]
|
||
|
|
""
|
||
|
|
"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
|
||
|
|
DONE;"
|
||
|
|
)
|
||
|
|
|
||
|
|
(define_expand "lshrsi3"
|
||
|
|
[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
|
||
|
|
(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
|
||
|
|
(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
|
||
|
|
(clobber (match_scratch:HI 3 ""))])]
|
||
|
|
""
|
||
|
|
"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
|
||
|
|
DONE;"
|
||
|
|
)
|