489 lines
16 KiB
Markdown
489 lines
16 KiB
Markdown
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;; Machine description for GNU compiler,
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;; for Atmel AVR micro controllers.
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;; Copyright (C) 1998-2021 Free Software Foundation, Inc.
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;; Contributed by Georg Lay (avr@gjlay.de)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The purpose of this file is to provide a light-weight DImode
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;; implementation for AVR. The trouble with DImode is that tree -> RTL
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;; lowering leads to really unpleasant code for operations that don't
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;; work byte-wise like NEG, PLUS, MINUS, etc. Defining optabs entries for
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;; them won't help because the optab machinery assumes these operations
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;; are cheap and does not check if a libgcc implementation is available.
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;;
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;; The DImode insns are all straight forward -- except movdi. The approach
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;; of this implementation is to provide DImode insns without the burden of
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;; introducing movdi.
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;;
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;; The caveat is that if there are insns for some mode, there must also be a
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;; respective move insn that describes reloads. Therefore, this
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;; implementation uses an accumulator-based model with two hard-coded,
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;; accumulator-like registers
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;;
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;; A[] = reg:DI 18
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;; B[] = reg:DI 10
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;;
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;; so that no DImode insn contains pseudos or needs reloading.
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(define_constants
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[(ACC_A 18)
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(ACC_B 10)])
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;; Supported modes that are 8 bytes wide
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(define_mode_iterator ALL8 [DI DQ UDQ DA UDA TA UTA])
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(define_mode_iterator ALL8U [UDQ UDA UTA])
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(define_mode_iterator ALL8S [ DQ DA TA])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Addition
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; "adddi3"
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;; "adddq3" "addudq3"
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;; "addda3" "adduda3"
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;; "addta3" "adduta3"
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(define_expand "add<mode>3"
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[(parallel [(match_operand:ALL8 0 "general_operand" "")
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(match_operand:ALL8 1 "general_operand" "")
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(match_operand:ALL8 2 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
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avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
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emit_move_insn (acc_a, operands[1]);
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if (DImode == <MODE>mode
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&& s8_operand (operands[2], VOIDmode))
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{
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emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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emit_insn (gen_adddi3_const8_insn ());
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}
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else if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_add<mode>3_const_insn (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
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emit_insn (gen_add<mode>3_insn ());
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}
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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;; "adddi3_insn"
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;; "adddq3_insn" "addudq3_insn"
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;; "addda3_insn" "adduda3_insn"
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;; "addta3_insn" "adduta3_insn"
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(define_insn "add<mode>3_insn"
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[(set (reg:ALL8 ACC_A)
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(plus:ALL8 (reg:ALL8 ACC_A)
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(reg:ALL8 ACC_B)))]
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"avr_have_dimode"
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"%~call __adddi3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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(define_insn "adddi3_const8_insn"
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[(set (reg:DI ACC_A)
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(plus:DI (reg:DI ACC_A)
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(sign_extend:DI (reg:QI REG_X))))]
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"avr_have_dimode"
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"%~call __adddi3_s8"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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;; "adddi3_const_insn"
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;; "adddq3_const_insn" "addudq3_const_insn"
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;; "addda3_const_insn" "adduda3_const_insn"
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;; "addta3_const_insn" "adduta3_const_insn"
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(define_insn "add<mode>3_const_insn"
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[(set (reg:ALL8 ACC_A)
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(plus:ALL8 (reg:ALL8 ACC_A)
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(match_operand:ALL8 0 "const_operand" "n Ynn")))]
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"avr_have_dimode
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&& !s8_operand (operands[0], VOIDmode)"
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{
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return avr_out_plus (insn, operands);
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}
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[(set_attr "adjust_len" "plus")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Subtraction
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; "subdi3"
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;; "subdq3" "subudq3"
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;; "subda3" "subuda3"
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;; "subta3" "subuta3"
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(define_expand "sub<mode>3"
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[(parallel [(match_operand:ALL8 0 "general_operand" "")
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(match_operand:ALL8 1 "general_operand" "")
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(match_operand:ALL8 2 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
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avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
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emit_move_insn (acc_a, operands[1]);
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if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_sub<mode>3_const_insn (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
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emit_insn (gen_sub<mode>3_insn ());
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}
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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;; "subdi3_insn"
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;; "subdq3_insn" "subudq3_insn"
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;; "subda3_insn" "subuda3_insn"
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;; "subta3_insn" "subuta3_insn"
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(define_insn "sub<mode>3_insn"
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[(set (reg:ALL8 ACC_A)
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(minus:ALL8 (reg:ALL8 ACC_A)
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(reg:ALL8 ACC_B)))]
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"avr_have_dimode"
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"%~call __subdi3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "set_czn")])
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;; "subdi3_const_insn"
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;; "subdq3_const_insn" "subudq3_const_insn"
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;; "subda3_const_insn" "subuda3_const_insn"
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;; "subta3_const_insn" "subuta3_const_insn"
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(define_insn "sub<mode>3_const_insn"
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[(set (reg:ALL8 ACC_A)
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(minus:ALL8 (reg:ALL8 ACC_A)
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(match_operand:ALL8 0 "const_operand" "n Ynn")))]
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"avr_have_dimode"
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{
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return avr_out_plus (insn, operands);
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}
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[(set_attr "adjust_len" "plus")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Signed Saturating Addition and Subtraction
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "<code_stdname><mode>3"
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[(set (match_operand:ALL8S 0 "general_operand" "")
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(ss_addsub:ALL8S (match_operand:ALL8S 1 "general_operand" "")
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(match_operand:ALL8S 2 "general_operand" "")))]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
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avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
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emit_move_insn (acc_a, operands[1]);
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if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_<code_stdname><mode>3_const_insn (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
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emit_insn (gen_<code_stdname><mode>3_insn ());
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}
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "<code_stdname><mode>3_insn"
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[(set (reg:ALL8S ACC_A)
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(ss_addsub:ALL8S (reg:ALL8S ACC_A)
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(reg:ALL8S ACC_B)))]
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"avr_have_dimode"
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"%~call __<code_stdname><mode>3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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(define_insn "<code_stdname><mode>3_const_insn"
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[(set (reg:ALL8S ACC_A)
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(ss_addsub:ALL8S (reg:ALL8S ACC_A)
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(match_operand:ALL8S 0 "const_operand" "n Ynn")))]
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"avr_have_dimode"
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{
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return avr_out_plus (insn, operands);
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}
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[(set_attr "adjust_len" "plus")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Unsigned Saturating Addition and Subtraction
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "<code_stdname><mode>3"
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[(set (match_operand:ALL8U 0 "general_operand" "")
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(us_addsub:ALL8U (match_operand:ALL8U 1 "general_operand" "")
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(match_operand:ALL8U 2 "general_operand" "")))]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
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avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
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emit_move_insn (acc_a, operands[1]);
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if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_<code_stdname><mode>3_const_insn (operands[2]));
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}
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else
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{
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emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
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emit_insn (gen_<code_stdname><mode>3_insn ());
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}
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "<code_stdname><mode>3_insn"
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[(set (reg:ALL8U ACC_A)
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(us_addsub:ALL8U (reg:ALL8U ACC_A)
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(reg:ALL8U ACC_B)))]
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"avr_have_dimode"
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"%~call __<code_stdname><mode>3"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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(define_insn "<code_stdname><mode>3_const_insn"
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[(set (reg:ALL8U ACC_A)
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(us_addsub:ALL8U (reg:ALL8U ACC_A)
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(match_operand:ALL8U 0 "const_operand" "n Ynn")))]
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"avr_have_dimode"
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{
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return avr_out_plus (insn, operands);
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}
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[(set_attr "adjust_len" "plus")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Negation
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "negdi2"
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[(parallel [(match_operand:DI 0 "general_operand" "")
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(match_operand:DI 1 "general_operand" "")])]
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"avr_have_dimode"
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{
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rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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emit_move_insn (acc_a, operands[1]);
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emit_insn (gen_negdi2_insn ());
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emit_move_insn (operands[0], acc_a);
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DONE;
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})
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(define_insn "negdi2_insn"
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[(set (reg:DI ACC_A)
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(neg:DI (reg:DI ACC_A)))]
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"avr_have_dimode"
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"%~call __negdi2"
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[(set_attr "adjust_len" "call")
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(set_attr "cc" "clobber")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Comparison
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "conditional_jump"
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[(set (pc)
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(if_then_else
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(match_operator 0 "ordered_comparison_operator" [(cc0)
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(const_int 0)])
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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"avr_have_dimode")
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;; "cbranchdi4"
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;; "cbranchdq4" "cbranchudq4"
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;; "cbranchda4" "cbranchuda4"
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;; "cbranchta4" "cbranchuta4"
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(define_expand "cbranch<mode>4"
|
||
|
|
[(parallel [(match_operand:ALL8 1 "register_operand" "")
|
||
|
|
(match_operand:ALL8 2 "nonmemory_operand" "")
|
||
|
|
(match_operator 0 "ordered_comparison_operator" [(cc0)
|
||
|
|
(const_int 0)])
|
||
|
|
(label_ref (match_operand 3 "" ""))])]
|
||
|
|
"avr_have_dimode"
|
||
|
|
{
|
||
|
|
rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
|
||
|
|
|
||
|
|
avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
|
||
|
|
emit_move_insn (acc_a, operands[1]);
|
||
|
|
|
||
|
|
if (s8_operand (operands[2], VOIDmode))
|
||
|
|
{
|
||
|
|
emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
|
||
|
|
emit_insn (gen_compare_const8_di2 ());
|
||
|
|
}
|
||
|
|
else if (const_operand (operands[2], GET_MODE (operands[2])))
|
||
|
|
{
|
||
|
|
emit_insn (gen_compare_const_<mode>2 (operands[2]));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
|
||
|
|
emit_insn (gen_compare_<mode>2 ());
|
||
|
|
}
|
||
|
|
|
||
|
|
emit_jump_insn (gen_conditional_jump (operands[0], operands[3]));
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
;; "compare_di2"
|
||
|
|
;; "compare_dq2" "compare_udq2"
|
||
|
|
;; "compare_da2" "compare_uda2"
|
||
|
|
;; "compare_ta2" "compare_uta2"
|
||
|
|
(define_insn "compare_<mode>2"
|
||
|
|
[(set (cc0)
|
||
|
|
(compare (reg:ALL8 ACC_A)
|
||
|
|
(reg:ALL8 ACC_B)))]
|
||
|
|
"avr_have_dimode"
|
||
|
|
"%~call __cmpdi2"
|
||
|
|
[(set_attr "adjust_len" "call")
|
||
|
|
(set_attr "cc" "compare")])
|
||
|
|
|
||
|
|
(define_insn "compare_const8_di2"
|
||
|
|
[(set (cc0)
|
||
|
|
(compare (reg:DI ACC_A)
|
||
|
|
(sign_extend:DI (reg:QI REG_X))))]
|
||
|
|
"avr_have_dimode"
|
||
|
|
"%~call __cmpdi2_s8"
|
||
|
|
[(set_attr "adjust_len" "call")
|
||
|
|
(set_attr "cc" "compare")])
|
||
|
|
|
||
|
|
;; "compare_const_di2"
|
||
|
|
;; "compare_const_dq2" "compare_const_udq2"
|
||
|
|
;; "compare_const_da2" "compare_const_uda2"
|
||
|
|
;; "compare_const_ta2" "compare_const_uta2"
|
||
|
|
(define_insn "compare_const_<mode>2"
|
||
|
|
[(set (cc0)
|
||
|
|
(compare (reg:ALL8 ACC_A)
|
||
|
|
(match_operand:ALL8 0 "const_operand" "n Ynn")))
|
||
|
|
(clobber (match_scratch:QI 1 "=&d"))]
|
||
|
|
"avr_have_dimode
|
||
|
|
&& !s8_operand (operands[0], VOIDmode)"
|
||
|
|
{
|
||
|
|
return avr_out_compare64 (insn, operands, NULL);
|
||
|
|
}
|
||
|
|
[(set_attr "adjust_len" "compare64")
|
||
|
|
(set_attr "cc" "compare")])
|
||
|
|
|
||
|
|
|
||
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||
|
|
;; Shifts and Rotate
|
||
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||
|
|
|
||
|
|
(define_code_iterator di_shifts
|
||
|
|
[ashift ashiftrt lshiftrt rotate])
|
||
|
|
|
||
|
|
;; Shift functions from libgcc are called without defining these insns,
|
||
|
|
;; but with them we can describe their reduced register footprint.
|
||
|
|
|
||
|
|
;; "ashldi3" "ashrdi3" "lshrdi3" "rotldi3"
|
||
|
|
;; "ashldq3" "ashrdq3" "lshrdq3" "rotldq3"
|
||
|
|
;; "ashlda3" "ashrda3" "lshrda3" "rotlda3"
|
||
|
|
;; "ashlta3" "ashrta3" "lshrta3" "rotlta3"
|
||
|
|
;; "ashludq3" "ashrudq3" "lshrudq3" "rotludq3"
|
||
|
|
;; "ashluda3" "ashruda3" "lshruda3" "rotluda3"
|
||
|
|
;; "ashluta3" "ashruta3" "lshruta3" "rotluta3"
|
||
|
|
(define_expand "<code_stdname><mode>3"
|
||
|
|
[(parallel [(match_operand:ALL8 0 "general_operand" "")
|
||
|
|
(di_shifts:ALL8 (match_operand:ALL8 1 "general_operand" "")
|
||
|
|
(match_operand:QI 2 "general_operand" ""))])]
|
||
|
|
"avr_have_dimode"
|
||
|
|
{
|
||
|
|
rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
|
||
|
|
|
||
|
|
avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
|
||
|
|
emit_move_insn (acc_a, operands[1]);
|
||
|
|
emit_move_insn (gen_rtx_REG (QImode, 16), operands[2]);
|
||
|
|
emit_insn (gen_<code_stdname><mode>3_insn ());
|
||
|
|
emit_move_insn (operands[0], acc_a);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
;; "ashldi3_insn" "ashrdi3_insn" "lshrdi3_insn" "rotldi3_insn"
|
||
|
|
;; "ashldq3_insn" "ashrdq3_insn" "lshrdq3_insn" "rotldq3_insn"
|
||
|
|
;; "ashlda3_insn" "ashrda3_insn" "lshrda3_insn" "rotlda3_insn"
|
||
|
|
;; "ashlta3_insn" "ashrta3_insn" "lshrta3_insn" "rotlta3_insn"
|
||
|
|
;; "ashludq3_insn" "ashrudq3_insn" "lshrudq3_insn" "rotludq3_insn"
|
||
|
|
;; "ashluda3_insn" "ashruda3_insn" "lshruda3_insn" "rotluda3_insn"
|
||
|
|
;; "ashluta3_insn" "ashruta3_insn" "lshruta3_insn" "rotluta3_insn"
|
||
|
|
(define_insn "<code_stdname><mode>3_insn"
|
||
|
|
[(set (reg:ALL8 ACC_A)
|
||
|
|
(di_shifts:ALL8 (reg:ALL8 ACC_A)
|
||
|
|
(reg:QI 16)))]
|
||
|
|
"avr_have_dimode"
|
||
|
|
"%~call __<code_stdname>di3"
|
||
|
|
[(set_attr "adjust_len" "call")
|
||
|
|
(set_attr "cc" "clobber")])
|
||
|
|
|
||
|
|
;; "umulsidi3"
|
||
|
|
;; "mulsidi3"
|
||
|
|
(define_expand "<extend_u>mulsidi3"
|
||
|
|
[(parallel [(match_operand:DI 0 "register_operand" "")
|
||
|
|
(match_operand:SI 1 "general_operand" "")
|
||
|
|
(match_operand:SI 2 "general_operand" "")
|
||
|
|
;; Just to mention the iterator
|
||
|
|
(clobber (any_extend:SI (match_dup 1)))])]
|
||
|
|
"avr_have_dimode
|
||
|
|
&& AVR_HAVE_MUL"
|
||
|
|
{
|
||
|
|
avr_fix_inputs (operands, 1 << 2, regmask (SImode, 22));
|
||
|
|
emit_move_insn (gen_rtx_REG (SImode, 22), operands[1]);
|
||
|
|
emit_move_insn (gen_rtx_REG (SImode, 18), operands[2]);
|
||
|
|
emit_insn (gen_<extend_u>mulsidi3_insn());
|
||
|
|
// Use emit_move_insn and not open-coded expand because of missing movdi
|
||
|
|
emit_move_insn (operands[0], gen_rtx_REG (DImode, ACC_A));
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
;; "umulsidi3_insn"
|
||
|
|
;; "mulsidi3_insn"
|
||
|
|
(define_insn "<extend_u>mulsidi3_insn"
|
||
|
|
[(set (reg:DI ACC_A)
|
||
|
|
(mult:DI (any_extend:DI (reg:SI 18))
|
||
|
|
(any_extend:DI (reg:SI 22))))
|
||
|
|
(clobber (reg:HI REG_X))
|
||
|
|
(clobber (reg:HI REG_Z))]
|
||
|
|
"avr_have_dimode
|
||
|
|
&& AVR_HAVE_MUL"
|
||
|
|
"%~call __<extend_u>mulsidi3"
|
||
|
|
[(set_attr "adjust_len" "call")
|
||
|
|
(set_attr "cc" "clobber")])
|